STOP: Core livelock buster

Using the FIT timer, periodically quiesce both cores to avoid
a livelock between two active cores

1) Mask SCOM RC=4 on the write to direct controls to stop the core
2) If core doesn't quiesce, abort and restart the core
3) Use the 32ns timebase to abort quiesce attempt after 200us
4) Add quiesce abort count to CME_Record
5) Make abort count a #define

Change-Id: Ibaf60e96350ba5d94d782ba6143df3e21004266f
Original-Change-Id: Idd50c7535bf343d7a8c1b7fb2ba0374349df5082
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45708
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c

@@ -555,6 +555,8 @@ p9_cme_stop_entry()
 
             // Permanent workaround for HW407385
 
+            wrteei(0);
+
             PK_TRACE("HW407385: Assert block interrupt to PC via SICR[2/3]");
             out32(CME_LCL_SICR_OR, core << SHIFT32(3));
 
@@ -567,6 +569,8 @@ p9_cme_stop_entry()
 
             while((in32(CME_LCL_EINR)) & (core << SHIFT32(21)));
 
+            wrteei(1);
+
             // end of HW407385
 
 #if HW402407_NDD1_TLBIE_STOP_WORKAROUND
@@ -710,6 +714,8 @@ p9_cme_stop_entry()
 
             // Permanent workaround for HW407385
 
+            wrteei(0);
+
             PK_TRACE("HW407385: Drop pm_exit via SICR[4/5]");
             out32(CME_LCL_SICR_CLR, core << SHIFT32(5));
 
@@ -723,6 +729,8 @@ p9_cme_stop_entry()
             PK_TRACE("HW407385: Drop block interrupt to PC via SICR[2/3]");
             out32(CME_LCL_SICR_CLR, core << SHIFT32(3));
 
+            wrteei(1);
+
             // end of HW407385
 
             //==========================