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STOP: Enable CHTM
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CHTM traces use Homer CpmrBase + 0x80000 + 16KB*cme_id
When enabled, the CHTM traces are hard coded to
0x20000000 + 16MB*EX

Change-Id: Id678b1813191a5668a4772571ffaa9cef192ebf4
Original-Change-Id: I80256273a0b7fc31c2f8b5119108ca34e1599106
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38437
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
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@davidduyue @op-jenkins
davidduyue authored and op-jenkins committed Aug 22, 2018
1 parent 595dfc6 commit 3a274b8
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Showing 2 changed files with 43 additions and 17 deletions.
15 changes: 15 additions & 0 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
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Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,7 @@ extern "C" {
#define RESTORE_RING_BITS(mask, ring, save) ring = (((ring) & (~mask)) | (save));
#endif


#define DEBUG_TRACE_CONTROL 0x100107D0
#define L3TRA_TRACE_TRCTRL_CONFIG 0x10010402
#define L3TRA_TRACE_TRDATA_CONFIG_0 0x10010403
Expand Down Expand Up @@ -139,6 +140,19 @@ extern "C" {
#define EX_PM_LCO_DIS_REG 0x10011816
#define EX_PM_L2_RCMD_DIS_REG 0x10011818

#define EX_CHTM0_MODE_REG 0x10012200
#define EX_CHTM1_MODE_REG 0x10012300
#define EX_CHTM0_MEM_REG 0x10012201
#define EX_CHTM1_MEM_REG 0x10012301
#define EX_CHTM0_STAT_REG 0x10012202
#define EX_CHTM1_STAT_REG 0x10012302
#define EX_CHTM0_LAST_REG 0x10012203
#define EX_CHTM1_LAST_REG 0x10012303
#define EX_CHTM0_TRIG_REG 0x10012204
#define EX_CHTM1_TRIG_REG 0x10012304
#define EX_CHTM0_CTRL_REG 0x10012205
#define EX_CHTM1_CTRL_REG 0x10012305

#define PERV_CPLT_CTRL0_OR 0x10000010
#define PERV_CPLT_CTRL0_CLEAR 0x10000020
#define PERV_CPLT_CTRL1_OR 0x10000011
Expand Down Expand Up @@ -205,6 +219,7 @@ enum SGPE_STOP_EVENT_LEVELS
enum SGPE_STOP_CME_FLAGS
{
CME_TRACE_ENABLE = BIT32(4),
CME_CHTM_ENABLE = BIT32(4),
CME_EX1_INDICATOR = BIT32(26),
CME_SIBLING_FUNCTIONAL = BIT32(27),
CME_CORE0_ENTRY_FIRST = BIT32(28),
Expand Down
45 changes: 28 additions & 17 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,7 @@ p9_sgpe_stop_entry()
int l3_purge_aborted = 0;
uint32_t ex = 0;
uint32_t ex_mask = 0;
uint32_t ex_index = 0;
uint32_t bitloc = 0;
uint32_t qloop = 0;
uint32_t cloop = 0;
Expand Down Expand Up @@ -574,26 +575,33 @@ p9_sgpe_stop_entry()

#if !SKIP_L3_PURGE

PK_TRACE("Assert purge L3 via EX_PM_PURGE_REG[0]");

if(ex & FST_EX_IN_QUAD)
for (ex_mask = 2; ex_mask; ex_mask--)
{
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 0), BIT64(0));
}
if (ex & ex_mask)
{
ex_index = ex_mask & 1;

if(ex & SND_EX_IN_QUAD)
{
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, 1), BIT64(0));
}
PK_TRACE("Assert purge L3 on EX[%d] via EX_PM_PURGE_REG[0]", ex_index);
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG, qloop, ex_index), BIT64(0));

// disable cme trace array
sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR);
PK_TRACE("Halt CHTM[0+1] on EX[%d] via HTM_TRIG[1]", ex_index);
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM0_TRIG_REG, qloop, ex_index), BIT64(1));
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM1_TRIG_REG, qloop, ex_index), BIT64(1));

if (pSgpeImgHdr->g_sgpe_reserve_flags & BIT32(4))
{
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, qloop), BIT64(1));
// Disable PMISC and IMA - Bits 1,2,4
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM0_CTRL_REG, qloop, ex_index), 0);
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM1_CTRL_REG, qloop, ex_index), 0);

// Disable Tracing
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM0_MODE_REG, qloop, ex_index), 0);
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_CHTM1_MODE_REG, qloop, ex_index), 0);

}
}

PK_TRACE("Disable cme trace array via DEBUG_TRACE_CONTROL[1]");
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, qloop), BIT64(1));

PK_TRACE("Poll for L3 purge done via EX_PM_PURGE_REG[0]");

// Poll on the same request bit thus no need to deassert
Expand Down Expand Up @@ -807,16 +815,18 @@ p9_sgpe_stop_entry()
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_DRAM_REF_REG, qloop, 1), scom_data.value);
}

PK_TRACE("Check NCU_SATUS_REG[0:3] for all zeros");
PK_TRACE("Check NCU_STATUS_REG[0:3] for all zeros");
// HW407207 - can only check bit 0:2

if (ex & FST_EX_IN_QUAD)
{
do
{
GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_STATUS_REG, qloop, 0),
scom_data.value);
PKTRACE("Polling NCU_STATUS_REG 0");
}
while(((~(scom_data.words.upper)) & BITS32(0, 4)) != BITS32(0, 4));
while(((~(scom_data.words.upper)) & BITS32(0, 3)) != BITS32(0, 3));
}

if (ex & SND_EX_IN_QUAD)
Expand All @@ -825,8 +835,9 @@ p9_sgpe_stop_entry()
{
GPE_GETSCOM(GPE_SCOM_ADDR_EX(EX_NCU_STATUS_REG, qloop, 1),
scom_data.value);
PKTRACE("Polling NCU_STATUS_REG 1");
}
while(((~(scom_data.words.upper)) & BITS32(0, 4)) != BITS32(0, 4));
while(((~(scom_data.words.upper)) & BITS32(0, 3)) != BITS32(0, 3));
}

PK_TRACE_DBG("NCU Status Clean");
Expand Down

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