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STOP Image updates
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This commit is pending to be regressed and merged.
Thus, freeze puting new change feature in unless
necessary fix to existing features.

1) add starting ANEP clock and
   drop ANEP regional fence before starting DPLL clock
2) change trace level to 1 by default
   change trace level 1 to only print tiny traces
   trace level 2 will print variable debug info
   trace level 3 will print all traces
3) use self restore address from header instead of hardcoded
4) enable dpll lock check when in lab
5) finish up lco settings in sgpe code
6) DTS enablement in stop/istep code
7) skip cache power off if hostAttn or localXstop
8) istep4 set special wakeup, sgpe remove when ready
9) disable dpll lock check as still work in progress
10)rebase
11)fix jenkins
12)fix db1 workaround on OR/CLR address
13)can write db1 base address directly instead of read first
14)fix self restore address fetch
15)clear pig type2/3/6 pending in sgpe setup
16)move hostAttn/localXstop read before stopclocks
17)fix typo in 16)
18)fix getscom(hostAttn/localXstop)
19)fix hrmor[13:42]

Change-Id: I5e235f245b4d73c68b8d8c7bcda3eefc40289b5a
Original-Change-Id: Ibde32271db0543661c426d8eed8531ba6312c6e5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32514
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
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@davidduyue @op-jenkins
davidduyue authored and op-jenkins committed Aug 22, 2018
1 parent 43ed89a commit 4d137bc
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Showing 3 changed files with 78 additions and 68 deletions.
24 changes: 12 additions & 12 deletions import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -92,14 +92,14 @@ p9_cme_stop_entry()
core = core & G_cme_stop_record.core_enabled &
G_cme_stop_record.core_running;

PK_TRACE_INF("Check: Core Select[%d] Enabled[%d] Running[%d]",
PK_TRACE_DBG("Check: Core Select[%d] Enabled[%d] Running[%d]",
core, G_cme_stop_record.core_enabled,
G_cme_stop_record.core_running);

if (!core)
{
// PM_ACTIVE can be phantom, only gives warning
PK_TRACE_INF("WARNING: No Valid PM_ACTIVE Signal Found. Return");
PK_TRACE_INF("WARNING: Only Phantom PM_ACTIVE to be Ignored. Return");
return CME_STOP_SUCCESS;
}

Expand Down Expand Up @@ -203,7 +203,7 @@ p9_cme_stop_entry()
}
}

PK_TRACE_INF("Check: Stop Levels Request[%d %d] Actual[%d, %d]",
PK_TRACE_DBG("Check: Stop Levels Request[%d %d] Actual[%d, %d]",
G_cme_stop_record.req_level_c0,
G_cme_stop_record.req_level_c1,
G_cme_stop_record.act_level_c0,
Expand All @@ -214,7 +214,7 @@ p9_cme_stop_entry()

if(core_stop1)
{
PK_TRACE_INF("Check: core[%d] core_stop1[%d]", core, core_stop1);
PK_TRACE_DBG("Check: core[%d] core_stop1[%d]", core, core_stop1);

#if HW386841_DD1_PLS_SRR1_DLS_STOP1_FIX

Expand Down Expand Up @@ -307,7 +307,7 @@ p9_cme_stop_entry()
STOP_ACT_DISABLE);
}

PK_TRACE_INF("Check: core[%d] target_lv[%d] deeper_lv[%d] deeper_core[%d]",
PK_TRACE_DBG("Check: core[%d] target_lv[%d] deeper_lv[%d] deeper_core[%d]",
core, target_level, deeper_level, deeper_core);

// Poll Infinitely for PCB Mux Grant
Expand Down Expand Up @@ -531,7 +531,7 @@ p9_cme_stop_entry()
//========================
}

PK_TRACE_INF("Catch: core[%d] running[%d] core_catchup[%d] origin_core[%d]",
PK_TRACE_DBG("Catch: core[%d] running[%d] core_catchup[%d] origin_core[%d]",
core, G_cme_stop_record.core_running, core_catchup, origin_core);

#endif
Expand Down Expand Up @@ -569,7 +569,7 @@ p9_cme_stop_entry()
core_aborted = core & G_cme_stop_record.core_running;
core = core & ~G_cme_stop_record.core_running;

PK_TRACE_INF("Abort: core[%d] running[%d] core_aborted[%d]",
PK_TRACE_DBG("Abort: core[%d] running[%d] core_aborted[%d]",
core, G_cme_stop_record.core_running, core_aborted);

if (!core)
Expand All @@ -589,7 +589,7 @@ p9_cme_stop_entry()
deeper_core = 0;
}

PK_TRACE_INF("Check: core[%d] deeper_core[%d] target_level[%d] deeper_level[%d]",
PK_TRACE_DBG("Check: core[%d] deeper_core[%d] target_level[%d] deeper_level[%d]",
core, deeper_core, target_level, deeper_level);

//----------------------------------------------------------------------
Expand Down Expand Up @@ -785,7 +785,7 @@ p9_cme_stop_entry()
core_aborted = core & G_cme_stop_record.core_running;
core = core & ~G_cme_stop_record.core_running;

PK_TRACE_INF("Abort: core[%d] running[%d] core_aborted[%d]",
PK_TRACE_DBG("Abort: core[%d] running[%d] core_aborted[%d]",
core, G_cme_stop_record.core_running, core_aborted);

if (!core)
Expand All @@ -805,7 +805,7 @@ p9_cme_stop_entry()
deeper_core = 0;
}

PK_TRACE_INF("Check: core[%d] deeper_core[%d] target_level[%d] deeper_level[%d]",
PK_TRACE_DBG("Check: core[%d] deeper_core[%d] target_level[%d] deeper_level[%d]",
core, deeper_core, target_level, deeper_level);

//----------------------------------------------------------------------
Expand Down Expand Up @@ -855,7 +855,7 @@ p9_cme_stop_entry()
MARK_TAG(SE_PURGE_L2_ABORT, core_aborted)
//=======================================

PK_TRACE_INF("Abort: L2+NCU purge aborted by core[%d]", core_aborted);
PK_TRACE_DBG("Abort: L2+NCU purge aborted by core[%d]", core_aborted);
out32(CME_LCL_SICR_OR, BIT32(19) | BIT32(23));
}

Expand Down Expand Up @@ -942,7 +942,7 @@ p9_cme_stop_entry()
PK_TRACE("Switch PPM wakeup to STOP-GPE via CPMMR[13]");
CME_PUTSCOM(CPPM_CPMMR_OR, core, BIT64(13));

PK_TRACE_INF("SE5.2B: Handed off to SGPE");
PK_TRACE_INF("SE5.B: Handed off to SGPE");

}
while(0);
Expand Down
23 changes: 7 additions & 16 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,13 +53,20 @@ extern "C" {

#include "p9_stop_common.h"

#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX
#define EXTRACT_RING_BITS(mask, ring, save) save = (ring) & (mask);
#define RESTORE_RING_BITS(mask, ring, save) ring = (((ring) & (~mask)) | (save));
#endif

#define EQ_RING_FENCE_MASK_LATCH 0x10010008
#define EQ_SYNC_CONFIG 0x10030000
#define EQ_OPCG_ALIGN 0x10030001
#define EQ_SCAN_REGION_TYPE 0x10030005
#define EQ_CLK_REGION 0x10030006
#define EQ_CLOCK_STAT_SL 0x10030008
#define EQ_CLOCK_STAT_ARY 0x1003000A
#define EQ_HOST_ATTN 0x10040009
#define EQ_LOCAL_XSTOP_ERR 0x10040018
#define EQ_THERM_MODE_REG 0x1005000F

#define EQ_BIST 0x100F000B
Expand Down Expand Up @@ -181,22 +188,6 @@ enum SGPE_STOP_VECTOR_INDEX
VECTOR_CONFIG = 2
};

#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX
#define EXTRACT_RING_BITS(mask, ring, save) save = (ring) & (mask);
#define RESTORE_RING_BITS(mask, ring, save) ring = (((ring) & (~mask)) | (save));
#endif

/// 64bits data
typedef union
{
uint64_t value;
struct
{
uint32_t upper;
uint32_t lower;
} words;
} data64_t;

typedef struct
{
// requested stop state calculated from core stop levels
Expand Down
99 changes: 59 additions & 40 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,8 @@ p9_sgpe_stop_entry()
uint32_t loop;
uint64_t scom_data;
uint64_t temp_data;
uint64_t host_attn;
uint64_t local_xstop;
ppm_sshsrc_t hist;
#if HW386311_DD1_PBIE_RW_PTR_STOP11_FIX
int spin;
Expand Down Expand Up @@ -138,18 +140,18 @@ p9_sgpe_stop_entry()
if (G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY] ||
G_sgpe_stop_record.group.quad[VECTOR_ENTRY])
{
PK_TRACE_INF("Actual: clv[%d][%d][%d][%d]",
PK_TRACE_DBG("Actual: clv[%d][%d][%d][%d]",
G_sgpe_stop_record.level[qloop][0],
G_sgpe_stop_record.level[qloop][1],
G_sgpe_stop_record.level[qloop][2],
G_sgpe_stop_record.level[qloop][3]);

PK_TRACE_INF("Actual: qlv:[%d]x0lv[%d]x1lv[%d]",
PK_TRACE_DBG("Actual: qlv:[%d]x0lv[%d]x1lv[%d]",
G_sgpe_stop_record.state[qloop].act_state_q,
G_sgpe_stop_record.state[qloop].act_state_x0,
G_sgpe_stop_record.state[qloop].act_state_x1);

PK_TRACE_INF("Request: qlv[%d]x0lv[%d]x1lv[%d]",
PK_TRACE_DBG("Request: qlv[%d]x0lv[%d]x1lv[%d]",
G_sgpe_stop_record.state[qloop].req_state_q,
G_sgpe_stop_record.state[qloop].req_state_x0,
G_sgpe_stop_record.state[qloop].req_state_x1);
Expand All @@ -165,7 +167,7 @@ p9_sgpe_stop_entry()
G_sgpe_stop_record.group.quad[VECTOR_ENTRY] &=
G_sgpe_stop_record.group.quad[VECTOR_CONFIG];

PK_TRACE_INF("Core Entry Vectors: X[%x] X0[%x] X1[%x] Q[%x]",
PK_TRACE_DBG("Core Entry Vectors: X[%x] X0[%x] X1[%x] Q[%x]",
G_sgpe_stop_record.group.ex_b[VECTOR_ENTRY],
G_sgpe_stop_record.group.ex_l[VECTOR_ENTRY],
G_sgpe_stop_record.group.ex_r[VECTOR_ENTRY],
Expand Down Expand Up @@ -202,7 +204,7 @@ p9_sgpe_stop_entry()
PK_TRACE_INF("+++++ +++++ EX STOP ENTRY [LEVEL 8-10] +++++ +++++");
// ------------------------------------------------------------------------

PK_TRACE_INF("Check: q[%d]ex[%d] start ex entry", qloop, ex);
PK_TRACE_DBG("Check: q[%d]ex[%d] start ex entry", qloop, ex);

PK_TRACE("Update QSSR: stop_entry_ongoing");
out32(OCB_QSSR_OR, BIT32(qloop + 20));
Expand Down Expand Up @@ -411,7 +413,7 @@ p9_sgpe_stop_entry()
ex |= SND_EX_IN_QUAD;
}

PK_TRACE_INF("Check: q[%d]ex[%d] starts quad entry", qloop, ex);
PK_TRACE_DBG("Check: q[%d]ex[%d] starts quad entry", qloop, ex);

PK_TRACE("Update QSSR: stop_entry_ongoing");
out32(OCB_QSSR_OR, BIT32(qloop + 20));
Expand Down Expand Up @@ -470,12 +472,12 @@ p9_sgpe_stop_entry()

if (in32(OCB_OISR1) & (BITS32(15, 2) | BIT32(19)))
{
PK_TRACE_INF("Abort: interrupt detected");
PK_TRACE("Abort: interrupt detected");

if ((in32(OCB_OPITNPRA(2)) & BITS32((qloop << 2), 4)) ||
(in32(OCB_OPITNPRA(3)) & BITS32((qloop << 2), 4)))
{
PK_TRACE_INF("Abort: core interrupt detected");
PK_TRACE("Abort: core interrupt detected");

for(cloop = 0; cloop < CORES_PER_QUAD; cloop++)
{
Expand Down Expand Up @@ -658,6 +660,16 @@ p9_sgpe_stop_entry()

PK_TRACE_INF("SE11.C: NCU Status Clean");

// In order to preserve state for PRD,
// skip power off if host attn or local xstop present
// Need to read status before stopclocks
// while these registers are still accessible
PK_TRACE("Checking status of Host Attention");
GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_HOST_ATTN, qloop), host_attn);

PK_TRACE("Checking status of Local Checkstop");
GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_LOCAL_XSTOP_ERR, qloop), local_xstop);

//===========================
MARK_TRAP(SE_STOP_CACHE_CLKS)
//===========================
Expand Down Expand Up @@ -793,7 +805,7 @@ p9_sgpe_stop_entry()
PK_TRACE("Assert vital thold via NET_CTRL0[16]");
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(16));

PK_TRACE("Shutdown L3[%d] EDRAM via QCCR[0-3/4-7]", ex);
PK_TRACE("Shutdown L3 EDRAM via QCCR[0-3/4-7]");
// QCCR[0/4] EDRAM_ENABLE_DC
// QCCR[1/5] EDRAM_VWL_ENABLE_DC
// QCCR[2/6] L3_EX0/1_EDRAM_VROW_VBLH_ENABLE_DC
Expand Down Expand Up @@ -825,45 +837,52 @@ p9_sgpe_stop_entry()

#if !STOP_PRIME

PK_TRACE("Drop vdd/vcs_pfet_val/sel_override/regulation_finger_en via PFCS[4-7,8]");
// vdd_pfet_val/sel_override = 0 (disbaled)
// vcs_pfet_val/sel_override = 0 (disbaled)
// vdd_pfet_regulation_finger_en = 0 (controled by FSM)
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, qloop),
BITS64(4, 4) | BIT64(8));
if ((host_attn | local_xstop) & BIT64(0))
{
PK_TRACE_INF("WARNING: HostAttn or LocalXstop Present, Skip Cache Power Off");
}
else
{
PK_TRACE("Drop vdd/vcs_pfet_val/sel_override/regulation_finger_en via PFCS[4-7,8]");
// vdd_pfet_val/sel_override = 0 (disbaled)
// vcs_pfet_val/sel_override = 0 (disbaled)
// vdd_pfet_regulation_finger_en = 0 (controled by FSM)
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, qloop),
BITS64(4, 4) | BIT64(8));

PK_TRACE("Power off VCS via PFCS[2-3]");
// vcs_pfet_force_state = 01 (Force Voff)
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, qloop), BIT64(3));
PK_TRACE("Power off VCS via PFCS[2-3]");
// vcs_pfet_force_state = 01 (Force Voff)
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, qloop), BIT64(3));

PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[50]");
// todo: poll the sense line instead
PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[50]");
// todo: poll the sense line instead

do
{
GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, qloop), scom_data);
}
while(!(scom_data & BIT64(50)));
do
{
GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, qloop), scom_data);
}
while(!(scom_data & BIT64(50)));

PK_TRACE("Power off VDD via PFCS[0-1]");
// vdd_pfet_force_state = 01 (Force Voff)
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, qloop), BIT64(1));
PK_TRACE("Power off VDD via PFCS[0-1]");
// vdd_pfet_force_state = 01 (Force Voff)
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, qloop), BIT64(1));

PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[42]");
// todo: poll the sense line instead
PK_TRACE("Poll for power gate sequencer state: 0x8 (FSM Idle) via PFCS[42]");
// todo: poll the sense line instead

do
{
GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, qloop), scom_data);
}
while(!(scom_data & BIT64(42)));
do
{
GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS, qloop), scom_data);
}
while(!(scom_data & BIT64(42)));

PK_TRACE("Turn off force voff via PFCS[0-3]");
// vdd_pfet_force_state = 00 (Nop)
// vcs_pfet_force_state = 00 (Nop)
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, qloop), BITS64(0, 4));
PK_TRACE("Turn off force voff via PFCS[0-3]");
// vdd_pfet_force_state = 00 (Nop)
// vcs_pfet_force_state = 00 (Nop)
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, qloop), BITS64(0, 4));

PK_TRACE_INF("SE11.E: Cache Powered Off");
PK_TRACE_INF("SE11.E: Cache Powered Off");
}

#endif

Expand Down

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