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CME/SGPE: STOP11 CME/SGPE Images Snapshot
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Change-Id: I551f77be3f1b77191b6ef9bdb2233b7ea52b8378
Original-Change-Id: I13d6c747e7b4b0b19e317ba7a5b74f852dee6ddf
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23571
Tested-by: Jenkins Server
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
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@davidduyue @op-jenkins
davidduyue authored and op-jenkins committed Aug 22, 2018
1 parent 64616b7 commit 5f2e6f8
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Showing 3 changed files with 52 additions and 17 deletions.
21 changes: 15 additions & 6 deletions import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
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Original file line number Diff line number Diff line change
Expand Up @@ -234,6 +234,7 @@ p9_cme_stop_entry()

PK_TRACE("SE2.j");
// Raise Core Chiplet Fence
CME_PUTSCOM(C_CPLT_CTRL0_OR, core, BIT64(2));
CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(18));

PK_TRACE("SE2.k");
Expand Down Expand Up @@ -280,10 +281,14 @@ p9_cme_stop_entry()

PK_TRACE("SE2.p");
// Switch glsmux to refclk to save clock grid power
CME_PUTSCOM(C_PPM_CGCR, core, BIT64(3));
CME_PUTSCOM(C_PPM_CGCR, core, 0);

// Assert PCB Fence
CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(25));
//CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(25));
// Assert Vital Fence
CME_PUTSCOM(C_CPLT_CTRL1_OR, core, BIT64(3));
// Assert Regional Fences
CME_PUTSCOM(C_CPLT_CTRL1_OR, core, 0xFFFF700000000000);

PK_TRACE("SE2.q");
// Update Stop History: In Core Stop Level 2
Expand Down Expand Up @@ -500,11 +505,14 @@ p9_cme_stop_entry()
MARK_TAG(SE_POWER_OFF_CORE, core)
//===============================

#if !STOP_PRIME
// Assert Cores Electrical Fences
// DD: Assert Cores Vital Thold/PCB Fence/Electrical Fence
PK_TRACE("SE4.a");
CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(25));
CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(26));
CME_PUTSCOM(CPPM_NC0INDIR_OR, core, BIT64(16));

#if !STOP_PRIME
#if !EPM_P9_TUNING
// Make sure we are not forcing PFET for VDD off
// vdd_pfet_force_state == 00 (Nop)
PK_TRACE("SE4.b");
Expand All @@ -515,6 +523,8 @@ p9_cme_stop_entry()
return CME_STOP_ENTRY_VDD_PFET_NOT_IDLE;
}

#endif

// Prepare PFET Controls
// vdd_pfet_val/sel_override = 0 (disbaled)
// vdd_pfet_regulation_finger_en = 0 (controled by FSM)
Expand Down Expand Up @@ -546,7 +556,6 @@ p9_cme_stop_entry()
while(!(scom_data & BIT64(46)));

#endif

// Turn Off Force Voff
// vdd_pfet_force_state = 00 (Nop)
PK_TRACE("SE4.g");
Expand Down Expand Up @@ -695,7 +704,7 @@ p9_cme_stop_entry()
//===========================
do
{
#if !SKIP_ABORT
#if !SKIP_L2_PURGE_ABORT

if(in32(CME_LCL_EINR) & BITS32(12, 6))
{
Expand Down
4 changes: 4 additions & 0 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
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Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,7 @@

#include "p9_stop_common.h"

#define EQ_SYNC_CONFIG 0x10030000
#define EQ_OPCG_ALIGN 0x10030001
#define EQ_SCAN_REGION_TYPE 0x10030005
#define EQ_CLK_REGION 0x10030006
Expand All @@ -57,11 +58,14 @@
#define EQ_BIST 0x100F000B
#define EQ_NET_CTRL0_WAND 0x100F0041
#define EQ_NET_CTRL0_WOR 0x100F0042
#define EQ_NET_CTRL1_WAND 0x100F0045
#define EQ_NET_CTRL1_WOR 0x100F0046

#define EQ_CPLT_CTRL0_OR 0x10000010
#define EQ_CPLT_CTRL0_CLEAR 0x10000020
#define EQ_CPLT_CTRL1_OR 0x10000011
#define EQ_CPLT_CTRL1_CLEAR 0x10000021
#define EQ_CPLT_STAT0 0x10000100

#define EQ_QPPM_DPLL_CTRL_CLEAR 0x100F0153
#define EQ_QPPM_DPLL_CTRL_OR 0x100F0154
Expand Down
44 changes: 33 additions & 11 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
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Original file line number Diff line number Diff line change
Expand Up @@ -97,6 +97,9 @@ p9_sgpe_stop_entry()
//========================

PK_TRACE("SE8.a");
// Assert L2 Regional Fences
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop),
((uint64_t)ex << SHIFT64(9)));
// Disable L2 Snoop(quiesce L2-L3 interface, what about NCU?)
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_L2_RCMD_DIS_REG, qloop, ex), BIT64(0));
PPE_WAIT_CORE_CYCLES(loop, 256)
Expand Down Expand Up @@ -273,6 +276,7 @@ p9_sgpe_stop_entry()
if (in32(OCB_OPIT2CN(((qloop << 2) + cloop))) &
TYPE2_PAYLOAD_STOP_EVENT)
{
MARK_TRAP(SE_PURGE_L3_ABORT)
// Assert Purge L3 Abort
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_PURGE_REG,
qloop, ex), BIT64(2));
Expand All @@ -285,6 +289,8 @@ p9_sgpe_stop_entry()
}
while(scom_data & (BIT64(0) | BIT64(2)));

MARK_TRAP(SE_PURGE_L3_ABORT_DONE)

// Deassert LCO Disable
GPE_PUTSCOM(GPE_SCOM_ADDR_EX(EX_PM_LCO_DIS_REG,
qloop, ex), 0);
Expand Down Expand Up @@ -369,6 +375,8 @@ p9_sgpe_stop_entry()
// todo: check NCU_SATUS_REG[0:3] for all zeros

PK_TRACE("SE11.k");
// Assert flush_inhibit
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL0_OR, qloop), BIT64(2));
// Raise Cache Logical fence
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(18));

Expand All @@ -379,7 +387,8 @@ p9_sgpe_stop_entry()

PK_TRACE("SE11.m");
// Stop Cache Clocks
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, qloop), 0x9F3E00000000E000);
//GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, qloop), 0x9F3E00000000E000);
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLK_REGION, qloop), 0x9E3E00000000E000);

PK_TRACE("SE11.n");

Expand All @@ -388,7 +397,9 @@ p9_sgpe_stop_entry()
{
GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_CLOCK_STAT_SL, qloop), scom_data);
}
while((scom_data & BITS64(4, 10)) != BITS64(4, 10));

//while((scom_data & (BITS64(4, 4) | BITS64(10, 4))) != (BITS64(4, 4) | BITS64(10, 4)));
while((scom_data & (BITS64(4, 3) | BITS64(10, 5))) != (BITS64(4, 3) | BITS64(10, 5)));

// MF: verify compiler generate single rlwmni
// MF: delay may be needed for stage latch to propagate thold
Expand All @@ -397,7 +408,12 @@ p9_sgpe_stop_entry()

PK_TRACE("SE11.o");
// Switch glsmux to refclk to save clock grid power
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, qloop), BIT64(3));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_PPM_CGCR, qloop), 0);
// Assert Vital Fence
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop), BIT64(3));
// Raise Partial Good Fences
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_CPLT_CTRL1_OR, qloop),
0xFFFF700000000000);

// Update QSSR: quad_stopped
out32(OCB_QSSR_OR, BIT32(qloop + 14));
Expand All @@ -414,22 +430,27 @@ p9_sgpe_stop_entry()
MARK_TAG(SE_POWER_OFF_CACHE, (32 >> qloop))
//========================================

// Assert Cache Electrical Fence
// DD: Assert Cache Vital Thold/PCB Fence/Electrical Fence
PK_TRACE("SE11.q");
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(25));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(26));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WOR, qloop), BIT64(16));

#if !STOP_PRIME
// L3 edram shutdown
PK_TRACE("SE11.r");
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(7));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(6));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(5));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(4));
/*
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(7));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(6));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(5));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(4));
*/
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(3));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(2));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(1));
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_QCCR_WCLEAR, qloop), BIT64(0));

#if !STOP_PRIME
#if !EPM_P9_TUNING
// Make sure we are not forcing PFET for VDD or VCS off
// vdd_pfet_force_state == 00 (Nop)
// vcs_pfet_force_state == 00 (Nop)
Expand All @@ -441,19 +462,20 @@ p9_sgpe_stop_entry()
return SGPE_STOP_ENTRY_VDD_PFET_NOT_IDLE;
}

#endif

// Prepare PFET Controls
// vdd_pfet_val/sel_override = 0 (disbaled)
// vcs_pfet_val/sel_override = 0 (disbaled)
// vdd_pfet_regulation_finger_en = 0 (controled by FSM)
PK_TRACE("SE11.t");
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_CLR, qloop), BITS64(4, 4) | BIT64(8));

// Power Off Core VDD
// Power Off Cache VDD/VDS
// vdd_pfet_force_state = 01 (Force Voff)
// vcs_pfet_force_state = 01 (Force Voff)
PK_TRACE("SE11.u");
GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_PFCS_OR, qloop), BIT64(1) | BIT64(3));

// Poll for power gate sequencer state: 0x8 (FSM Idle)
PK_TRACE("SE11.v");

Expand Down

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