STOP: Fix Resonent Clock Support for STOP11

1) modify the CME pstate resonant clock adjustment code to
1a) have better detection for the issue being fixed.
1b) to read cme flag at runtime for whether to touch
    resonant clock setting due to pstate change

2) modify the CME DB2 Handler to
1a) when disable resonant clock for stop11, also disable
    pstate code from changing the setting via cme flags
1b) when stop11 is aborted, and DB2 is asked to restore
    the resonant clock setting, also enable pstate to do so

3) modify the SGPE PIG Handler to
1a) fix the bug that one quad has resonant clock ready for
    stop11 entry or exit, the code automaticially grant
    ready for other quads
1b) fix the bug that resonant clock ready PIG will result an
    redundant IPC sent to PGPE for the core already IPCed

4) Modify the SGPE entry code to
   fix the bug that other quad calling entry service can
   result this quad doing an redundant stop11 entry after
   exam again the previous resonant clock ready state.

5) Fix compiler flag to continue using NDD20 code on NDD21+
   until the NDD21 code is ready (skewadjust issue)

6) Like 2) above, Fix Sibling needs to disable pstate code
   from reenabling resonant clock when going into stop11
   also the restore measure for Sibling

7) Fix interrupt window condition to cause pstate code
   to pass the rclk_operatable check and change rclk
   when db2 interrupt to disable pstate from change rclk
   happening after the check condition but before change

8) fixing partial good case when writing to cme flags

9) db2 read using single cast instead of dual cast

10) using unique panic code for additional error detection

11) Fix PGPE and CME conflict on PMSR writes

12) revert Marker change and remove redundant critial section

Change-Id: Ibcedaff1a1aa7cded1dc1c0944bacb77b3e67d14
Original-Change-Id: I70d86686be690f030dfa4886875c4fa00dcae208
CQ: SW404802
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46775
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>

import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c

@@ -89,6 +89,7 @@ p9_sgpe_stop_entry()
 #if DISABLE_STOP8
 
              G_sgpe_stop_record.group.quad[VECTOR_RCLKE]  |
+             G_sgpe_stop_record.group.quad[VECTOR_RCLKX]  |
 
 #endif
 
@@ -181,11 +182,13 @@ p9_sgpe_stop_entry()
 
                 // assume ex0 core0 is good
                 cindex = (qloop << 2);
+                ex = 0;
 
                 // if ex0 is bad, switch to ex1
                 if (!(G_sgpe_stop_record.group.expg[qloop] & FST_EX_IN_QUAD))
                 {
                     cindex += 2;
+                    ex = 1;
                 }
 
                 // if first core in the ex is bad
@@ -197,6 +200,17 @@ p9_sgpe_stop_entry()
                 // send DB2 with msgid 0x2 to the first good core
                 // to trigger Quad Manager to disable resonant clock
 
+                // QM will also clear the cme_flag[rclk_operatable] to
+                // temporarily disable pstate code from changing rclk
+                // but the Sibling CME also needs to do so, here SGPE
+                // will do it for the Sibling.
+
+                if (G_sgpe_stop_record.group.expg[qloop] & (ex + 1))
+                {
+                    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS_CLR, qloop, (ex ^ 1)),
+                                BIT64(CME_FLAGS_RCLK_OPERABLE));
+                }
+
 #if NIMBUS_DD_LEVEL != 10
 
                 GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CMEDB2, cindex), BIT64(6));
@@ -903,6 +917,16 @@ p9_sgpe_stop_entry()
 
         PK_TRACE_DBG("CME Halted");
 
+        GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QACCR, qloop), scom_data.value);
+
+        if (scom_data.words.upper)
+        {
+            // Stop11 needs resclk to be off, otherwise exit will fail
+            PK_TRACE_INF("ERROR: Q[%d]ACCR[%x] is not clean after CMEs are halted",
+                         qloop, scom_data.words.upper);
+            PK_PANIC(SGPE_STOP_ENTRY_STOP11_RESCLK_ON);
+        }
+
         //Set Quad GPMMR RESET_STATE_INDICATOR bit to indicate CME is offline
         GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_OR, qloop), BIT64(15));