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PGPE: Use global literals for reg addrs
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    Key_Cronus_Test=PM_REGRESS

Change-Id: I1e38eca3b888dde64b953e977efff887013dbd5e
CQ: SW428872
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60114
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
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@rbatraAustinIBM @op-jenkins
rbatraAustinIBM authored and op-jenkins committed Jun 8, 2018
1 parent 57f645d commit 85e6dce
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Showing 12 changed files with 141 additions and 103 deletions.
14 changes: 7 additions & 7 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/avs_driver.c
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Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,7 @@ uint8_t pollVoltageTransDone(void)
uint32_t ocbRegReadData = 0;
uint8_t ongoingFlag = 1;
uint8_t count = 0;
uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;

// The point of MAX_POLL_COUNT_AVS is to verify that ongoingFlag turns to
// zero very fast. Otherwise, something wrong with this i/f and error out.
Expand Down Expand Up @@ -124,7 +124,7 @@ uint8_t driveIdleFrame(void)
{
uint8_t rc = 0;
uint32_t idleframe = 0xFFFFFFFF;
uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;

// Clear sticky bits in o2s_status_reg
out32(OCB_O2SCMD0A | BusMask , 0x40000000);
Expand All @@ -148,12 +148,12 @@ uint8_t driveWrite(uint32_t CmdDataType, uint32_t CmdData)
uint32_t ocbRegWriteData = 0;
uint32_t ocbRegReadData = 0;

uint32_t RailSelect = in32(OCB_OCCS2) & AVS_RAIL_NUM_MASK;
uint32_t RailSelect = in32(G_OCB_OCCS2) & AVS_RAIL_NUM_MASK;
uint32_t StartCode = 1;
uint32_t CmdType = 0; // 0:write+commit, 1:write+hold, 2: d/c, 3:read
uint32_t CmdGroup = 0;
uint32_t CRC = 0;
uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;

// Clear sticky bits in o2s_status_reg
out32(OCB_O2SCMD0A | BusMask, 0x40000000);
Expand Down Expand Up @@ -228,14 +228,14 @@ uint8_t driveRead(uint32_t CmdDataType, uint32_t* CmdData)
uint32_t ocbRegReadData = 0;
uint32_t ocbRegWriteData = 0;

uint32_t RailSelect = in32(OCB_OCCS2) & AVS_RAIL_NUM_MASK;
uint32_t RailSelect = in32(G_OCB_OCCS2) & AVS_RAIL_NUM_MASK;
uint32_t StartCode = 1;
uint32_t CmdType = 3; // 0:write+commit, 1:write+hold, 2: d/c, 3:read
uint32_t CmdGroup = 0;
uint32_t Reserved = 0xFFFF;
uint32_t CRC = 0;

uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;

// Clear sticky bits in o2s_status_reg
out32(OCB_O2SCMD0A | BusMask, 0x40000000);
Expand Down Expand Up @@ -328,7 +328,7 @@ void external_voltage_control_init(uint32_t* vext_read_mv)
// OCI to SPIPMBus (O2S) bridge initialization
//

uint32_t BusMask = (in32(OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;
uint32_t BusMask = (in32(G_OCB_OCCS2) & AVS_BUS_NUM_MASK) << 4;

// O2SCTRLF
ocbRegReadData = in32(OCB_O2SCTRLF0A | BusMask);
Expand Down
15 changes: 14 additions & 1 deletion import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
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Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,7 @@ enum PGPE_WOF_CTRL
(QUAD0_EX1_MASK >> (q*2))

#define PGPE_OPTIONAL_TRACE_AND_PANIC(panic_code) \
if (in32(OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) { \
if (in32(G_OCB_OCCS2) & BIT32(PM_DEBUG_HALT_ENABLE)) { \
G_pgpe_optrace_data.word[0] = panic_code; \
p9_pgpe_optrace(HALT_CONDITION ); \
PK_PANIC(panic_code); }
Expand All @@ -121,6 +121,19 @@ enum PGPE_WOF_CTRL
PK_PANIC(panic_code);


extern uint32_t G_OCB_QCSR;
extern uint32_t G_OCB_OCCS2;
extern uint32_t G_OCB_OCCFLG;
extern uint32_t G_OCB_OCCFLG_OR;
extern uint32_t G_OCB_OCCFLG_CLR;
extern uint32_t G_OCB_OCCFLG2;
extern uint32_t G_OCB_OISR0_CLR;
extern uint32_t G_OCB_OIMR1_OR;
extern uint32_t G_OCB_OIMR1_CLR;
extern uint32_t G_OCB_OIMR0_OR;
extern uint32_t G_OCB_OIMR0_CLR;


/// PGPE PState
void p9_pgpe_irq_handler_occ_sgpe_cme_pvref_error(void* arg, PkIrqId irq);
void p9_pgpe_irq_handler_system_xstop(void* arg, PkIrqId irq);
Expand Down
20 changes: 10 additions & 10 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
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Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,7 @@ void p9_pgpe_fit_init()

__attribute__((always_inline)) inline void handle_core_throttle()
{
uint32_t config = in32(OCB_OCCS2); //bits 16-18 in OCC Scratch Register 2
uint32_t config = in32(G_OCB_OCCS2); //bits 16-18 in OCC Scratch Register 2
uint32_t run = (config >> 14) & 0x3; //this looks at the inject and enable bits, if either are high we run

if(run) //Currently running
Expand Down Expand Up @@ -146,7 +146,7 @@ __attribute__((always_inline)) inline void handle_core_throttle()

if(inject == 1)
{
out32(OCB_OCCS2, (config & 0xFFFFBFFF)); //write out to indicate inject has finished
out32(G_OCB_OCCS2, (config & 0xFFFFBFFF)); //write out to indicate inject has finished
}
}

Expand All @@ -169,7 +169,7 @@ __attribute__((always_inline)) inline void handle_quad_hb_update()
{
uint32_t q;
ocb_qcsr_t qcsr;
qcsr.value = in32(OCB_QCSR);
qcsr.value = in32(G_OCB_QCSR);

for (q = 0; q < MAX_QUADS; q++)
{
Expand Down Expand Up @@ -209,9 +209,9 @@ __attribute__((always_inline)) inline void handle_occflg_requests()
{
ocb_occflg_t occFlag;
//Read OCC_FLAGS
occFlag.value = in32(OCB_OCCFLG);
occFlag.value = in32(G_OCB_OCCFLG);

if(in32(OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_FIT_ERR_INJ))
if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_FIT_ERR_INJ))
{
PK_TRACE_ERR("FIT_IPC_ERROR_INJECT TRAP");
PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
Expand Down Expand Up @@ -243,9 +243,9 @@ __attribute__((always_inline)) inline void handle_occflg_requests()
//set error bit
if(G_pgpe_pstate_record.pstatesStatus != PSTATE_ACTIVE)
{
uint32_t occScr2 = in32(OCB_OCCS2);
uint32_t occScr2 = in32(G_OCB_OCCS2);
occScr2 |= BIT32(PGPE_SAFE_MODE_ERROR);
out32(OCB_OCCS2, occScr2);
out32(G_OCB_OCCS2, occScr2);
}
//Otherwise, process safe mode request
else
Expand All @@ -269,9 +269,9 @@ __attribute__((always_inline)) inline void handle_occflg_requests()
//number of FIT interrupts
__attribute__((always_inline)) inline void handle_aux_task()
{
if(in32(OCB_OCCFLG) & BIT32(AUX_THREAD_ACTIVATE))
if(in32(G_OCB_OCCFLG) & BIT32(AUX_THREAD_ACTIVATE))
{
out32(OCB_OCCFLG_OR, BIT32(AUX_THREAD_ACTIVE));
out32(G_OCB_OCCFLG_OR, BIT32(AUX_THREAD_ACTIVE));

if(G_aux_task_count == G_aux_task_count_threshold)
{
Expand All @@ -285,7 +285,7 @@ __attribute__((always_inline)) inline void handle_aux_task()
}
else
{
out32(OCB_OCCFLG_CLR, BIT32(AUX_THREAD_ACTIVE));
out32(G_OCB_OCCFLG_CLR, BIT32(AUX_THREAD_ACTIVE));
}
}

Expand Down
2 changes: 1 addition & 1 deletion import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c
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Original file line number Diff line number Diff line change
Expand Up @@ -153,7 +153,7 @@ void p9_pgpe_ipc_405_set_pmcr(ipc_msg_t* cmd, void* arg)
{
PK_TRACE_INF("IPC: Set PMCR");

if(in32(OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
{
PK_TRACE_ERR("SET PMCR IPC ERROR INJECT TRAP");
PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
Expand Down
16 changes: 8 additions & 8 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -173,8 +173,8 @@ void pk_irq_save_and_set_mask(uint32_t iPrtyLvl)
// the OIMR to a known value when we exit our thread.
if (++g_oimr_stack_ctr < NUM_EXT_IRQ_PRTY_LEVELS)
{
//prev: g_oimr_stack[g_oimr_stack_ctr] = ((uint64_t)in32(OCB_OIMR0))<<32 |
// (uint64_t)in32(OCB_OIMR1);
//prev: g_oimr_stack[g_oimr_stack_ctr] = ((uint64_t)in32(G_OCB_OIMR0))<<32 |
// (uint64_t)in32(G_OCB_OIMR1);
// Make a note of present prty level and then update tracker to new prty level.
g_oimr_stack[g_oimr_stack_ctr] = g_current_prty_level;
g_current_prty_level = iPrtyLvl; // Update prty level tracker.
Expand All @@ -192,16 +192,16 @@ void pk_irq_save_and_set_mask(uint32_t iPrtyLvl)
// This includes all those IRQs which belong to this instance as well as
// those high-prty IRQs shared with the other instances.
//
out32(OCB_OIMR0_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS >> 32));
out32(OCB_OIMR1_CLR, (uint32_t)IRQ_VEC_ALL_OUR_IRQS);
out32(G_OCB_OIMR0_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS >> 32));
out32(G_OCB_OIMR1_CLR, (uint32_t)IRQ_VEC_ALL_OUR_IRQS);

// Second, mask IRQs belonging to this task and lower prty tasks.
// Note, that we do not modify the permanently disabled IRQs, such as the
// _RESERVED_ ones. Nor do we touch other instances' IRQs. Iow, the
// IDX_PRTY_LVL_DISABLED mask is NOT part of the mask we apply below.
out32(OCB_OIMR0_OR, (uint32_t)((ext_irq_vectors_gpe[iPrtyLvl][IDX_MASK_VEC] |
g_oimr_override) >> 32) );
out32(OCB_OIMR1_OR, (uint32_t)(ext_irq_vectors_gpe[iPrtyLvl][IDX_MASK_VEC] |
g_oimr_override) );
out32(G_OCB_OIMR0_OR, (uint32_t)((ext_irq_vectors_gpe[iPrtyLvl][IDX_MASK_VEC] |
g_oimr_override) >> 32) );
out32(G_OCB_OIMR1_OR, (uint32_t)(ext_irq_vectors_gpe[iPrtyLvl][IDX_MASK_VEC] |
g_oimr_override) );

}
17 changes: 11 additions & 6 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,11 @@
#ifndef _P9_PGPE_IRQ_H_
#define _P9_PGPE_IRQ_H_

extern uint32_t G_OCB_OIMR1_OR;
extern uint32_t G_OCB_OIMR1_CLR;
extern uint32_t G_OCB_OIMR0_OR;
extern uint32_t G_OCB_OIMR0_CLR;

// We define four levels of TRACE outputs:
// _INF: Trace level used for main informational events.
// _DBG: Trace level used for expanded debugging.
Expand Down Expand Up @@ -114,14 +119,14 @@ pk_irq_vec_restore( PkMachineContext* context)

if (g_oimr_stack_ctr >= 0)
{
out32( OCB_OIMR0_CLR, (uint32_t)((IRQ_VEC_ALL_OUR_IRQS |
g_oimr_override_stack[g_oimr_stack_ctr]) >> 32));
out32( OCB_OIMR1_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS |
g_oimr_override_stack[g_oimr_stack_ctr]));
out32( OCB_OIMR0_OR,
out32( G_OCB_OIMR0_CLR, (uint32_t)((IRQ_VEC_ALL_OUR_IRQS |
g_oimr_override_stack[g_oimr_stack_ctr]) >> 32));
out32( G_OCB_OIMR1_CLR, (uint32_t)(IRQ_VEC_ALL_OUR_IRQS |
g_oimr_override_stack[g_oimr_stack_ctr]));
out32( G_OCB_OIMR0_OR,
(uint32_t)((ext_irq_vectors_gpe[g_oimr_stack[g_oimr_stack_ctr]][IDX_MASK_VEC] |
g_oimr_override) >> 32));
out32( OCB_OIMR1_OR,
out32( G_OCB_OIMR1_OR,
(uint32_t)(ext_irq_vectors_gpe[g_oimr_stack[g_oimr_stack_ctr]][IDX_MASK_VEC] |
g_oimr_override));
// Restore the prty level tracker to the task that was interrupted, if any.
Expand Down
28 changes: 14 additions & 14 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -56,8 +56,8 @@ void p9_pgpe_irq_init()
p9_pgpe_ocb_hb_error_init();

//Setup SGPE_ERR(OISR[8]) and PVREF_ERR(OISR[20])
out32(OCB_OISR0_CLR, BIT32(8) | BIT32(20));//Clear any pending interrupts
out32(OCB_OIMR0_CLR, BIT32(8) | BIT32(20));//Unmask interrupts
out32(G_OCB_OISR0_CLR, BIT32(8) | BIT32(20));//Clear any pending interrupts
out32(G_OCB_OIMR0_CLR, BIT32(8) | BIT32(20));//Unmask interrupts
}

//
Expand Down Expand Up @@ -86,8 +86,8 @@ void p9_pgpe_ocb_hb_error_init()

out64(OCB_OCCHBR, 0); //Clear and Disable OCC Heartbeat Register
GPE_PUTSCOM(OCB_OCCLFIR_AND, ~BIT64(OCC_HB_ERROR_FIR));
out32(OCB_OISR0_CLR, BIT32(2));//Clear any pending interrupts
out32(OCB_OIMR0_CLR, BIT32(2));//Unmask interrupt
out32(G_OCB_OISR0_CLR, BIT32(2));//Clear any pending interrupts
out32(G_OCB_OIMR0_CLR, BIT32(2));//Unmask interrupt
}

//
Expand Down Expand Up @@ -145,7 +145,7 @@ void p9_pgpe_irq_handler_ocb_err()

PK_TRACE_INF("OCB FIR Detected");

out32(OCB_OISR0_CLR, BIT32(2));
out32(G_OCB_OISR0_CLR, BIT32(2));

PGPE_OPTIONAL_TRACE_AND_PANIC(PGPE_OCC_FIR_IRQ);

Expand Down Expand Up @@ -188,8 +188,8 @@ void p9_pgpe_irq_handler_sgpe_err()
PK_TRACE_INF("SGPE Error");

g_oimr_override |= BIT64(8);
out32(OCB_OIMR0_OR, BIT32(8));
out32(OCB_OISR0_CLR, BIT32(8));
out32(G_OCB_OIMR0_OR, BIT32(8));
out32(G_OCB_OISR0_CLR, BIT32(8));

//Optrace
G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) |
Expand Down Expand Up @@ -226,7 +226,7 @@ void p9_pgpe_irq_handler_pvref_err()
{
PK_TRACE_INF("PVREF Error");

out32(OCB_OISR0_CLR, BIT32(20));
out32(G_OCB_OISR0_CLR, BIT32(20));

//Optrace
G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) |
Expand Down Expand Up @@ -265,8 +265,8 @@ void p9_pgpe_irq_handler_system_xstop(void* arg, PkIrqId irq)
PkMachineContext ctx;

g_oimr_override |= BIT64(15);
out32(OCB_OIMR0_OR, BIT32(15));
out32(OCB_OISR0_CLR, BIT32(15));
out32(G_OCB_OIMR0_OR, BIT32(15));
out32(G_OCB_OISR0_CLR, BIT32(15));

//Optrace
G_pgpe_optrace_data.word[0] = (G_pgpe_pstate_record.activeQuads << 24) |
Expand Down Expand Up @@ -296,7 +296,7 @@ void p9_pgpe_irq_handler_pcb_type1(void* arg, PkIrqId irq)
uint32_t c;
uint32_t opit1pra;

if(in32(OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
{
PK_TRACE_ERR("PCB TYPE1 ERROR INJECT TRAP");
PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
Expand Down Expand Up @@ -425,7 +425,7 @@ void p9_pgpe_irq_handler_cme_err()
uint64_t value, baseVal;
qppm_dpll_freq_t dpllFreq;
ocb_qcsr_t qcsr;
qcsr.value = in32(OCB_QCSR);
qcsr.value = in32(G_OCB_QCSR);
uint64_t cme_flags = 0;

//Optrace
Expand All @@ -444,7 +444,7 @@ void p9_pgpe_irq_handler_cme_err()
PK_TRACE_INF("CER:CME ERR opit5pr 0x%x", opit5pr);

//If prolonged droop recovery is not active
if (!(in32(OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
if (!(in32(G_OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
{
p9_pgpe_pstate_write_core_throttle(CORE_IFU_THROTTLE, RETRY);
}
Expand Down Expand Up @@ -564,7 +564,7 @@ void p9_pgpe_irq_handler_cme_err()
}

//If prolonged droop recovery is not active
if (!(in32(OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
if (!(in32(G_OCB_OCCFLG) & BIT32(PGPE_PROLONGED_DROOP_WORKAROUND_ACTIVE)))
{
p9_pgpe_pstate_write_core_throttle(CORE_THROTTLE_OFF, RETRY);
}
Expand Down
29 changes: 25 additions & 4 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,27 @@ PgpePstateRecord G_pgpe_pstate_record __attribute__((section (".dump_ptrs"))) =
};


//We define a global literal for these register addresses
//This way compiler put them in .sdata area, and the address
//can be loaded with one instruction using r13 as offset into
//sdata area. The change helped save about 448 bytes of code space.
//Note, some register's address were not moved to using global literals
//because in some cases they registers are accessed few times or they are
//used inside a loop. In both cases, either no code reduction was observed
//or resulted in code increase.
uint32_t G_OCB_QCSR = OCB_QCSR;
uint32_t G_OCB_OCCS2 = OCB_OCCS2;
uint32_t G_OCB_OCCFLG = OCB_OCCFLG;
uint32_t G_OCB_OCCFLG_OR = OCB_OCCFLG_OR;
uint32_t G_OCB_OCCFLG_CLR = OCB_OCCFLG_CLR;
uint32_t G_OCB_OCCFLG2 = OCB_OCCFLG2;
uint32_t G_OCB_OISR0_CLR = OCB_OISR0_CLR;
uint32_t G_OCB_OIMR0_OR = OCB_OIMR0_OR;
uint32_t G_OCB_OIMR1_OR = OCB_OIMR1_OR;
uint32_t G_OCB_OIMR0_CLR = OCB_OIMR0_CLR;
uint32_t G_OCB_OIMR1_CLR = OCB_OIMR1_CLR;


EXTERNAL_IRQ_TABLE_START
IRQ_HANDLER_DEFAULT //OCCHW_IRQ_DEBUGGER
IRQ_HANDLER_DEFAULT //OCCHW_IRQ_TRACE_TRIGGER
Expand Down Expand Up @@ -193,7 +214,7 @@ main(int argc, char** argv)
timebase);

// Read OCC_SCRATCH[PGPE_DEBUG_TRAP_ENABLE]
uint32_t occScr2 = in32(OCB_OCCS2);
uint32_t occScr2 = in32(G_OCB_OCCS2);

if (occScr2 & BIT32(PGPE_DEBUG_TRAP_ENABLE))
{
Expand All @@ -203,8 +224,8 @@ main(int argc, char** argv)

PK_TRACE("Clear OCC LFIR[gpe2_halted] and OISR[gpe2_error and xstop] bits upon PGPE boot");
GPE_PUTSCOM(OCB_OCCLFIR_AND, ~BIT64(24));
out32(OCB_OISR0_CLR, (BIT32(7) | BIT32(15)));
out32(OCB_OIMR0_CLR, (BIT32(7) | BIT32(15)));
out32(G_OCB_OISR0_CLR, (BIT32(7) | BIT32(15)));
out32(G_OCB_OIMR0_CLR, (BIT32(7) | BIT32(15)));

// Initialize the thread control block for G_p9_pgpe_thread_process_requests
pk_thread_create(&G_p9_pgpe_thread_process_requests,
Expand Down Expand Up @@ -265,7 +286,7 @@ main(int argc, char** argv)
p9_pgpe_irq_init();

g_oimr_override |= BIT64(49);
out32(OCB_OIMR1_OR, BIT32(17)); //Disable PCB_INTR_TYPE4
out32(G_OCB_OIMR1_OR, BIT32(17)); //Disable PCB_INTR_TYPE4

p9_pgpe_optrace_init();

Expand Down

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