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Hcode: hcode changes for STOP exit in SMF enabled HV mode
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Commit addresses STOP exit issue in HV mode with SMF enabled
from hcode perspective. Self-save restore binary is fixed to
so that on STOP exit core enters linux in HV mode with
SMFCTRL[E] bit SET.

Change-Id: I8f1c9ab5181786a39efd53453e02e16295a87b36
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87552
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
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@premsjha @op-jenkins
premsjha authored and op-jenkins committed Jan 18, 2020
1 parent 065c07c commit 9eca207
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Showing 5 changed files with 195 additions and 101 deletions.
31 changes: 17 additions & 14 deletions import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c
View file
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HCODE Project */
/* */
/* COPYRIGHT 2015,2019 */
/* COPYRIGHT 2015,2020 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -1162,6 +1162,8 @@ p9_cme_stop_self_execute(uint32_t core, uint32_t i_saveRestore )
{
uint32_t core_mask;
data64_t scom_data;
data64_t stop_exit_privilege;
stop_exit_privilege.value = 0;
cmeHeader_t* pCmeImgHdr = (cmeHeader_t*)(CME_SRAM_HEADER_ADDR);
scom_data.value = pCmeImgHdr->g_cme_cpmr_PhyAddr & BITS64(13, 30); //HRMOR[13:42]

Expand Down Expand Up @@ -1254,11 +1256,8 @@ p9_cme_stop_self_execute(uint32_t core, uint32_t i_saveRestore )
PK_TRACE_INF("SMF core wakes up, write URMOR with HOMER address" );
scom_data.words.upper = scom_data.words.upper & ~BIT32(15);

if( SPR_SELF_SAVE == i_saveRestore )
{
scom_data.value = pCmeImgHdr->g_cme_unsec_cpmr_PhyAddr & BITS64(13, 30); //Unsecure HOMER
PKTRACE("SMF core self save, write un-secure HOMER address");
}
scom_data.value = pCmeImgHdr->g_cme_unsec_cpmr_PhyAddr & BITS64(13, 30); //Unsecure HOMER
PKTRACE("SMF core self save, write un-secure HOMER address");

CME_PUTSCOM(HRMOR, core, scom_data.value);

Expand Down Expand Up @@ -1305,33 +1304,37 @@ p9_cme_stop_self_execute(uint32_t core, uint32_t i_saveRestore )
{
//Writing thread scratch register to
//Signal Self Save Restore code for save operation.
scom_data.words.upper = 0;
scom_data.words.lower = 1;
stop_exit_privilege.words.upper = 0;
stop_exit_privilege.words.lower = 1;
}
else
{
//Writing thread scratch register to
// 1. Init Runtime wakeup mode for core.
// 2. Signal Self Save Restore code for restore operation.
// 2. HV Exit with SMF enable or Disable
// 3. Signal Self Save Restore code for restore operation.


if (scom_data.words.upper & BIT32(3))
{
scom_data.value = BIT64(59);
stop_exit_privilege.value = BIT64(59);
}
else

if (scom_data.words.upper & BIT32(4))
{
scom_data.value = 0;
stop_exit_privilege.value |= BIT64(58);
}

}

if( CME_MASK_C0 & core_mask )
{
CME_PUTSCOM(SCRATCH0, CME_MASK_C0, scom_data.value);
CME_PUTSCOM(SCRATCH0, CME_MASK_C0, stop_exit_privilege.value);
}

if( CME_MASK_C1 & core_mask )
{
CME_PUTSCOM(SCRATCH1, CME_MASK_C1, scom_data.value);
CME_PUTSCOM(SCRATCH1, CME_MASK_C1, stop_exit_privilege.value);
}
}
}
Expand Down
54 changes: 44 additions & 10 deletions import/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.S
View file
Expand Up @@ -156,6 +156,8 @@
.set SMFCTRL_ENABLE_BIT, 0
.set MSR_SECURITY_BIT, 41
.set SCRATCH_RUNTIME_MODE_BIT, 59
.set HV_EXIT_WITH_SMF_ENABLE_BIT, 58 #0 : HV exit with SMFCTRL[E] bit SET to 0b01
#1 : HV exit with SMFCTRL[E] bit SET to 0b00

.set OTHER_THREADS_STOPPED, 0x07
.set CORE_THREAD_STATE_REG_ID, 0x01E0
Expand All @@ -178,6 +180,8 @@
.set RFID, 0x2400004c
.set TRAP_LE, 0x0800e07f
.set MFMSR_R21, 0xa600a07e
.set OFFSET_SMF_EN_SLAVE_THREADS, 0x04
.set SECURE_ADDR_BIT, 0x0f


.set SPR_SAVE_SCRATCH_REG, r0
Expand Down Expand Up @@ -759,25 +763,54 @@ mtsrr1 TEMP_REG2
mfspr TEMP_REG2, HSRR1
insrdi TEMP_REG2, TEMP_REG1, 1, MSR_SECURITY_BIT
mtspr HSRR1, TEMP_REG2
mfspr SMF_VAL_REG, SMFCTRL
insrdi SMF_VAL_REG, TEMP_REG1, 1, SMFCTRL_ENABLE_BIT
insrdi MSR_INIT_REG, TEMP_REG1, 1, MSR_SECURITY_BIT

addi TEMP_REG1, RMOR_INIT_REG, HRMOR_RESTORE_OFFSET
extrdi. TEMP_REG2, THREAD_SCRATCH_VAL_REG, 1, HV_EXIT_WITH_SMF_ENABLE_BIT
beq wakeup_hv_smf_enable_mode

wakeup_hv_smf_disable_mode:
insrdi SMF_VAL_REG, TEMP_REG1, 1, SMFCTRL_ENABLE_BIT
mtspr SMFCTRL, SMF_VAL_REG #SMFCTRL[E] is cleared

#In this case HOMER is expected in regular unsecure region.
li TEMP_REG2, HRMOR_RESTORE_OFFSET
cmplwi THREAD_ID_REG, 0
bne update_usrrx
addi TEMP_REG2, TEMP_REG2, SKIP_HRMOR_UPDATE_OFFSET # branch where slave threads STOPs
b update_usrrx

wakeup_hv_smf_enable_mode:
mfspr TEMP_REG2, URMOR #Check if Un-Secure HOMER location
extrdi. TEMP_REG1, TEMP_REG2, 1, SECURE_ADDR_BIT
cmplwi TEMP_REG1, 0
beq ipl_stop_exit

runtime_stop_exit:
mfspr TEMP_REG2, HRMOR #Get Un-Secure HOMER location
ori TEMP_REG2, TEMP_REG2, 0x200 #Exit Routine Offset
mtspr HRMOR, TEMP_REG2
b hrmor_restore_hv

#In an SMF enabled system, for compatbility reasons, during IPL HOMER is built in regular memory
#and gets moved to secure memory later during HOMER rebuild pahse. However, in istep 16 cores exits STOP
#in UV mode. Code below support HV exit just in case it is useful.

ipl_stop_exit:
li TEMP_REG2, HRMOR_RESTORE_OFFSET

hrmor_restore_hv:

cmplwi THREAD_ID_REG, 0
beq update_usrrx
addi TEMP_REG1, TEMP_REG1, SKIP_HRMOR_UPDATE_OFFSET # restore HRMOR only if thread0
addi TEMP_REG2, TEMP_REG2, OFFSET_SMF_EN_SLAVE_THREADS # branch where slave threads STOPs

update_usrrx:
mtspr USRR0, TEMP_REG1
mtspr USRR1, MSR_INIT_REG
cmpwi THREAD_ID_REG, 0
bne exit_to_thread_stop
mtspr USRR0, TEMP_REG2
mtspr USRR1, MSR_INIT_REG
mtspr SRR1, MSR_INIT_REG

#------------------------------ Trampoline Sequence Start -------------------------------

mtspr SMFCTRL, SMF_VAL_REG #SMFCTRL[E] = 0b0 for HV exit and 0b1 for UV exit

exit_to_thread_stop:
isync
.long urfid
Expand Down Expand Up @@ -810,6 +843,7 @@ mtspr USRR1, MSR_INIT_REG
.long urfid
.long ATTN


# THREAD_LAUNCHER_SIZE_OFFSET must be >= (4 * number of instructions between
# here and thread_launcher_start)

Expand Down
56 changes: 45 additions & 11 deletions import/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.s
View file
Expand Up @@ -22,10 +22,10 @@
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG
# 1 "/esw/san2/premjha2/ekbTest/ekb/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.S"
# 1 "/esw/san2/premjha2/ekbTest/p9_ekb/ekb/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.S"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "/esw/san2/premjha2/ekbTest/ekb/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.S"
# 1 "/esw/san2/premjha2/ekbTest/p9_ekb/ekb/chips/p9/procedures/utils/stopreg/p9_core_save_restore_routines.S"

.set r0, 0
.set r1, 1
Expand Down Expand Up @@ -160,6 +160,8 @@
.set SMFCTRL_ENABLE_BIT, 0
.set MSR_SECURITY_BIT, 41
.set SCRATCH_RUNTIME_MODE_BIT, 59
.set HV_EXIT_WITH_SMF_ENABLE_BIT, 58 #0 : HV exit with SMFCTRL[E] bit SET to 0b01
#1 : HV exit with SMFCTRL[E] bit SET to 0b00

.set OTHER_THREADS_STOPPED, 0x07
.set CORE_THREAD_STATE_REG_ID, 0x01E0
Expand All @@ -182,6 +184,8 @@
.set RFID, 0x2400004c
.set TRAP_LE, 0x0800e07f
.set MFMSR_R21, 0xa600a07e
.set OFFSET_SMF_EN_SLAVE_THREADS, 0x04
.set SECURE_ADDR_BIT, 0x0f


.set SPR_SAVE_SCRATCH_REG, r0
Expand Down Expand Up @@ -763,25 +767,54 @@ mtsrr1 TEMP_REG2
mfspr TEMP_REG2, HSRR1
insrdi TEMP_REG2, TEMP_REG1, 1, MSR_SECURITY_BIT
mtspr HSRR1, TEMP_REG2
mfspr SMF_VAL_REG, SMFCTRL
insrdi SMF_VAL_REG, TEMP_REG1, 1, SMFCTRL_ENABLE_BIT
insrdi MSR_INIT_REG, TEMP_REG1, 1, MSR_SECURITY_BIT

addi TEMP_REG1, RMOR_INIT_REG, HRMOR_RESTORE_OFFSET
extrdi. TEMP_REG2, THREAD_SCRATCH_VAL_REG, 1, HV_EXIT_WITH_SMF_ENABLE_BIT
beq wakeup_hv_smf_enable_mode

wakeup_hv_smf_disable_mode:
insrdi SMF_VAL_REG, TEMP_REG1, 1, SMFCTRL_ENABLE_BIT
mtspr SMFCTRL, SMF_VAL_REG #SMFCTRL[E] is cleared

#In this case HOMER is expected in regular unsecure region.
li TEMP_REG2, HRMOR_RESTORE_OFFSET
cmplwi THREAD_ID_REG, 0
bne update_usrrx
addi TEMP_REG2, TEMP_REG2, SKIP_HRMOR_UPDATE_OFFSET # branch where slave threads STOPs
b update_usrrx

wakeup_hv_smf_enable_mode:
mfspr TEMP_REG2, URMOR #Check if Un-Secure HOMER location
extrdi. TEMP_REG1, TEMP_REG2, 1, SECURE_ADDR_BIT
cmplwi TEMP_REG1, 0
beq ipl_stop_exit

runtime_stop_exit:
mfspr TEMP_REG2, HRMOR #Get Un-Secure HOMER location
ori TEMP_REG2, TEMP_REG2, 0x200 #Exit Routine Offset
mtspr HRMOR, TEMP_REG2
b hrmor_restore_hv

#In an SMF enabled system, for compatbility reasons, during IPL HOMER is built in regular memory
#and gets moved to secure memory later during HOMER rebuild pahse. However, in istep 16 cores exits STOP
#in UV mode. Code below support HV exit just in case it is useful.

ipl_stop_exit:
li TEMP_REG2, HRMOR_RESTORE_OFFSET

hrmor_restore_hv:

cmplwi THREAD_ID_REG, 0
beq update_usrrx
addi TEMP_REG1, TEMP_REG1, SKIP_HRMOR_UPDATE_OFFSET # restore HRMOR only if thread0
addi TEMP_REG2, TEMP_REG2, OFFSET_SMF_EN_SLAVE_THREADS # branch where slave threads STOPs

update_usrrx:
mtspr USRR0, TEMP_REG1
mtspr USRR0, TEMP_REG2
mtspr USRR1, MSR_INIT_REG
cmpwi THREAD_ID_REG, 0
bne exit_to_thread_stop
mtspr SRR1, MSR_INIT_REG

#------------------------------ Trampoline Sequence Start -------------------------------

mtspr SMFCTRL, SMF_VAL_REG #SMFCTRL[E] = 0b0 for HV exit and 0b1 for UV exit

exit_to_thread_stop:
isync
.long urfid
Expand Down Expand Up @@ -814,6 +847,7 @@ mtspr USRR1, MSR_INIT_REG
.long urfid
.long ATTN


# THREAD_LAUNCHER_SIZE_OFFSET must be >= (4 * number of instructions between
# here and thread_launcher_start)

Expand Down

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