UV Support : Augmented STOP API and self restore for enabling ultravi…

…sor. HW-Image-Coreq: yes HW-Image-Prereq: Ia9ae0d284398af375f1562efff152a6a12a6eb9a Change-Id: I1f7ca865640dfc0a08aef783fd3595d2f249a672 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/58843 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
open-power · Sep 26, 2018 · c919d9d · c919d9d
1 parent 0ee2ed1
commit c919d9d
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Showing 6 changed files with 802 additions and 105 deletions.
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -311,6 +311,7 @@ HCD_CONST(CPMR_ATTN_WORD1_BYTE,                 0x04)
 HCD_CONST(CPMR_MAGIC_NUMBER_BYTE,               0x08)
 HCD_CONST(CPMR_BUILD_DATE_BYTE,                 0x10)
 HCD_CONST(CPMR_BUILD_VER_BYTE,                  0x14)
+HCD_CONST(CPMR_URMOR_FIX_BYTE,                  0x1E)
 HCD_CONST(CPMR_CME_HCODE_OFFSET_BYTE,           0x20)
 HCD_CONST(CPMR_CME_HCODE_LENGTH_BYTE,           0x24)
 HCD_CONST(CPMR_CORE_COMMON_RING_OFFSET_BYTE,    0x28)
@@ -329,21 +330,30 @@ HCD_CONST(CPMR_MAX_SCOM_REST_PER_CORE_BYTE,     0x50)
 
 HCD_CONST(SELF_RESTORE_CPMR_OFFSET,             CPMR_HEADER_SIZE)
 HCD_CONST(SELF_RESTORE_INT_SIZE,                (8 * ONE_KB))
-HCD_CONST(THREAD_LAUNCHER_SIZE,                 256)
+HCD_CONST(THREAD_LAUNCHER_SIZE,                 1024)
 HCD_CONST(SELF_RESTORE_CODE_SIZE,
           (SELF_RESTORE_INT_SIZE + THREAD_LAUNCHER_SIZE))
 
-HCD_CONST(CORE_RESTORE_THREAD_AREA_SIZE,        (ONE_KB))
-HCD_CONST(CORE_RESTORE_CORE_AREA_SIZE,          (ONE_KB))
+HCD_CONST(CORE_RESTORE_THREAD_AREA_SIZE,         HALF_KB)
+HCD_CONST(SELF_SAVE_THREAD_AREA_SIZE,            256)
+HCD_CONST(CORE_RESTORE_CORE_AREA_SIZE,           HALF_KB)
+HCD_CONST(CORE_SAVE_CORE_AREA_SIZE,              HALF_KB)
+
+//self save-restore size per thread
 HCD_CONST(CORE_RESTORE_SIZE_PER_THREAD,
-          (CORE_RESTORE_THREAD_AREA_SIZE + CORE_RESTORE_CORE_AREA_SIZE))
+          (CORE_RESTORE_THREAD_AREA_SIZE + SELF_SAVE_THREAD_AREA_SIZE))
+//self save-restore size per core
+HCD_CONST(SELF_RESTORE_SIZE_PER_CORE,
+          (CORE_RESTORE_SIZE_PER_THREAD + CORE_RESTORE_CORE_AREA_SIZE +
+           CORE_SAVE_CORE_AREA_SIZE))
+//size of self restore region for entire chip
 HCD_CONST(SELF_RESTORE_CORE_REGS_SIZE,
-          (CORE_RESTORE_SIZE_PER_THREAD*
-           MAX_THREADS_PER_CORE* MAX_CORES_PER_CHIP))
-
+          (SELF_RESTORE_SIZE_PER_CORE* MAX_CORES_PER_CHIP))
+//total self restore region including thread launcher code size
 HCD_CONST(SELF_RESTORE_SIZE_TOTAL,
           (SELF_RESTORE_CODE_SIZE + SELF_RESTORE_CORE_REGS_SIZE))
 
+HCD_CONST( EC_LEVEL_URMOR_FIX, 0x23 )
 
 /// Core Scom
 

diff --git a/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H b/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HCODE Project                                                */
 /*                                                                        */
-/* COPYRIGHT 2015,2017                                                    */
+/* COPYRIGHT 2015,2018                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -50,21 +50,32 @@ namespace stopImageSection
  */
 enum
 {
-    ORI_OPCODE        = 24,
-    RFI_OPCODE        = 19,
-    RFI_CONST         = 50,
-    ORIS_OPCODE       = 25,
-    OPCODE_31         = 31,
-    XOR_CONST         = 316,
-    RLDICR_OPCODE     = 30,
-    RLDICR_CONST      = 1,
-    MTSPR_CONST1      = 467,
-    MTMSRD_CONST1     = 178,
-    MR_R0_TO_R10      = 0x7c0a0378, //mr r10, r0
-    MR_R0_TO_R21      = 0x7c150378, //mr r21, r0
-    BLR_INST          = 0x4e800020,
-    MTSPR_BASE_OPCODE = 0x7c0003a6,
-    ATTN_OPCODE       = 0x00000200,
+    ORI_OPCODE          =   24,
+    RFI_OPCODE          =   19,
+    RFI_CONST           =   50,
+    MFMSR_CONST         =   83,
+    ORIS_OPCODE         =   25,
+    OPCODE_31           =   31,
+    XOR_CONST           =   316,
+    RLDICR_OPCODE       =   30,
+    RLDICR_CONST        =   1,
+    MTSPR_CONST1        =   467,
+    MTMSRD_CONST1       =   178,
+    MR_R0_TO_R10        =   0x7c0a0378, //mr r10, r0
+    MR_R0_TO_R21        =   0x7c150378, //mr r21, r0
+    MR_R0_TO_R9         =   0x7c090378, //mr r9, r0
+    URMOR_CORRECTION    =   0x7d397ba6,
+    MFSPR_CONST         =   339,
+    BLR_INST            =   0x4e800020,
+    MTSPR_BASE_OPCODE   =   0x7c0003a6,
+    ATTN_OPCODE         =   0x00000200,
+    OPCODE_18           =   18,
+    SELF_SAVE_FUNC_ADD  =   0x2300,
+    SELF_SAVE_OFFSET    =   0x180,
+    SKIP_SPR_REST_INST  =   0x4800001c, //b . +0x01c
+    MFLR_R30            =   0x7fc802a6,
+    SKIP_SPR_SELF_SAVE  =   0x3bff0020, //addi r31 r31, 0x20
+    MTLR_INST           =   0x7fc803a6  //mtlr r30
 };
 
 #ifdef __cplusplus