Skip to content

Commit

Permalink
PM: clear Hcode error injection bits upon injection and malf alert
Browse files Browse the repository at this point in the history 
- Also deals with PM callout order issue with the malf alert assertion

Key_Cronus_Test=PM_REGRESS

Change-Id: I78b41c59d09369c60891beb41ff9debc986e59b4
CQ: SW434547
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61020
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
  • Loading branch information
@stillgs @op-jenkins
stillgs authored and op-jenkins committed Jun 26, 2018
1 parent e5489c3 commit dc65a49
Show file tree
Hide file tree
Showing 12 changed files with 89 additions and 10 deletions.
2 changes: 2 additions & 0 deletions import/chips/p9/procedures/ppe_closed/cme/pstate_cme/p9_cme_thread_db.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -587,6 +587,8 @@ void p9_cme_pstate_process_db0()

if( scom_data & BIT64(CPPM_CSAR_PSTATE_HCODE_ERROR_INJECT) )
{
// Clear the injection so things are not permenently stuck
CME_PUTSCOM(CPPM_CSAR_CLR, CME_MASK_BC, BIT64(CPPM_CSAR_PSTATE_HCODE_ERROR_INJECT));
PK_TRACE_ERR("CME PSTATE ERROR INJECT TRAP");
PK_PANIC(CME_PSTATE_TRAP_INJECT);
}
Expand Down
2 changes: 2 additions & 0 deletions import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1368,6 +1368,8 @@ p9_cme_stop_entry()

if( BIT64(CPPM_CSAR_STOP_HCODE_ERROR_INJECT) & scom_data.value )
{
// Clear the injection so things are not permenently stuck
CME_PUTSCOM(CPPM_CSAR_CLR, core, BIT64(CPPM_CSAR_STOP_HCODE_ERROR_INJECT));
PK_TRACE_DBG("CME STOP ENTRY ERROR INJECT TRAP");
PK_PANIC(CME_STOP_ENTRY_TRAP_INJECT);
}
Expand Down
81 changes: 71 additions & 10 deletions import/chips/p9/procedures/ppe_closed/lib/p9_stop_recovery_trigger.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,8 @@
#include "ppe42_scom.h"
#include "ppehw_common.h"
#include "gpehw_common.h"
#include "ocb_firmware_registers.h"
#include "cppm_register_addresses.h"
#include "ocb_register_addresses.h"
#include "p9_pm_hcd_flags.h"
#include "p9_stop_recovery_trigger.h"
Expand All @@ -39,32 +41,91 @@
void
p9_stop_recovery_trigger()
{
data64_t scom_data = {0};
uint32_t qloop = 0;
uint32_t cloop = 0;
uint32_t cindex = 0;
uint32_t m_1c = 0;
ocb_ccsr_t ccsr = {0};

// Clear ALL the error injections to have any hope that the next
// special wake-up will succeed. These have to be done first to
// avoid races with Hypervisors setting special wake-ups

// SGPE and PGPE.
scom_data.words.upper = BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ) |
BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ) |
BIT32(OCCFLG2_PGPE_HCODE_FIT_ERR_INJ);
out64(OCB_OCCFLG2_CLR, scom_data.value);

// CMEs
// The in-progress bit are not checked as this is an error case
ccsr.value = in32(OCB_CCSR);

for(qloop = 0;
qloop < MAX_QUADS;
qloop++)
{
for(cloop = 0; cloop < CORES_PER_QUAD; cloop++)
{
scom_data.value = 0;
cindex = (qloop << 2) + cloop;
m_1c = BIT32(cindex);

if(ccsr.value & m_1c)
{
PK_TRACE_DBG("core[%d][%d] error inject being cleared", qloop, cindex);
scom_data.words.upper = BIT32(CPPM_CSAR_FIT_HCODE_ERROR_INJECT) |
BIT32(CPPM_CSAR_PSTATE_HCODE_ERROR_INJECT) |
BIT32(CPPM_CSAR_STOP_HCODE_ERROR_INJECT);
GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(CPPM_CSAR_CLR, cindex), scom_data.value);
}
}
}

if (in32(OCB_OCCFLG2) & BIT32(STOP_RECOVERY_TRIGGER_ENABLE))
{
uint64_t scom_data = 0;
PK_TRACE_INF("WARNING: STOP RECOVERY TRIGGER!");

PK_TRACE("1. Set ADU lock for exclusive use for a timeout of 500ms.");
// Has to be set first to avoid races with Hypervisors reading
// this bit
PK_TRACE("1. Set OCCFLG2[28] PM Callout Active");
out32(OCB_OCCFLG2_OR, BIT32(PM_CALLOUT_ACTIVE));

PK_TRACE("2. Set ADU lock for exclusive use for a timeout of 500ms.");

do
{

GPE_PUTSCOM(0x90001, 0x0010000000000000ull);
GPE_GETSCOM(0x90001, scom_data);

GPE_GETSCOM(0x90001, scom_data.value);
}
while (!(scom_data & 0x0010000000000000ull));
while (!(scom_data.value & 0x0010000000000000ull));

PK_TRACE("2. Cleanup/reset ADU");
PK_TRACE("3. Cleanup/reset ADU");
// 3 Clear Status
// 4 Reset FSM
// 11 Locked
GPE_PUTSCOM(0x90001, 0x1810000000000000ull);

PK_TRACE("3. Setup PowerBus 'address' field for malf alert");
PK_TRACE("4. Setup PowerBus 'address' field for malf alert");
// 10 Set Malfunction Alert Error
GPE_PUTSCOM(0x90000, 0x0000100000000000ull);

PK_TRACE("4. Setup PowerBus command type and launch malfunction");
// 2 Start Op
// 6 AX Type
// 11 Locked
// 16:18 Scope 16:18 = VG = 101.
// 25:31 TType = 011 0100
// 32:39 TSize = 0000 0100 = 2B
GPE_PUTSCOM(0x90001, 0x2210A03104000000ull);

PK_TRACE("5. Set OCCFLG2[28] PM Callout Active");
out32(OCB_OCCFLG2_OR, BIT32(PM_CALLOUT_ACTIVE));
PK_TRACE("5. Cleanup/reset ADU");
// See above
GPE_PUTSCOM(0x90001, 0x1810000000000000ull);

PK_TRACE("6: Unlock ADU");
// 11 Clear to remove lock
GPE_PUTSCOM(0x90001, 0x0000000000000000ull);
}
}
1 change: 1 addition & 0 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,7 @@ extern uint32_t G_OCB_OCCFLG;
extern uint32_t G_OCB_OCCFLG_OR;
extern uint32_t G_OCB_OCCFLG_CLR;
extern uint32_t G_OCB_OCCFLG2;
extern uint32_t G_OCB_OCCFLG2_CLR;
extern uint32_t G_OCB_OISR0_CLR;
extern uint32_t G_OCB_OIMR1_OR;
extern uint32_t G_OCB_OIMR1_CLR;
Expand Down
2 changes: 2 additions & 0 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_fit.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -244,6 +244,8 @@ __attribute__((always_inline)) inline void handle_occflg_requests()

if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_FIT_ERR_INJ))
{
// Clear the injection so things are not permenently stuck
out32(G_OCB_OCCFLG2_CLR, BIT32(OCCFLG2_PGPE_HCODE_FIT_ERR_INJ));
PK_TRACE_ERR("FIT_IPC_ERROR_INJECT TRAP");
PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
}
Expand Down
2 changes: 2 additions & 0 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -175,6 +175,8 @@ void p9_pgpe_ipc_405_set_pmcr(ipc_msg_t* cmd, void* arg)

if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
{
// Clear the injection so things are not permenently stuck
out32(G_OCB_OCCFLG2_CLR, BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ));
PK_TRACE_ERR("SET PMCR IPC ERROR INJECT TRAP");
PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
}
Expand Down
2 changes: 2 additions & 0 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -306,6 +306,8 @@ void p9_pgpe_irq_handler_pcb_type1(void* arg, PkIrqId irq)
//If error injection bit is set in OCC Scratch 2, then halt PGPE immediately
if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
{
// Clear the injection so things are not permenently stuck
out32(G_OCB_OCCFLG2_CLR, BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ));
PK_TRACE_ERR("PCB TYPE1 ERROR INJECT TRAP");
PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
}
Expand Down
1 change: 1 addition & 0 deletions import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -91,6 +91,7 @@ uint32_t G_OCB_OCCFLG = OCB_OCCFLG;
uint32_t G_OCB_OCCFLG_OR = OCB_OCCFLG_OR;
uint32_t G_OCB_OCCFLG_CLR = OCB_OCCFLG_CLR;
uint32_t G_OCB_OCCFLG2 = OCB_OCCFLG2;
uint32_t G_OCB_OCCFLG2_CLR = OCB_OCCFLG2_CLR;
uint32_t G_OCB_OISR0_CLR = OCB_OISR0_CLR;
uint32_t G_OCB_OIMR0_OR = OCB_OIMR0_OR;
uint32_t G_OCB_OIMR1_OR = OCB_OIMR1_OR;
Expand Down
1 change: 1 addition & 0 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,7 @@ uint32_t G_OCB_OCCFLG = OCB_OCCFLG;
uint32_t G_OCB_OCCFLG_CLR = OCB_OCCFLG_CLR;
uint32_t G_OCB_OCCFLG_OR = OCB_OCCFLG_OR;
uint32_t G_OCB_OCCFLG2 = OCB_OCCFLG2;
uint32_t G_OCB_OCCFLG2_CLR = OCB_OCCFLG2_CLR;
uint32_t G_OCB_OCCS2 = OCB_OCCS2;
uint32_t G_OCB_OISR0_CLR = OCB_OISR0_CLR;
uint32_t G_OCB_OISR1 = OCB_OISR1;
Expand Down
1 change: 1 addition & 0 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,7 @@ extern uint32_t G_OCB_OCCFLG;
extern uint32_t G_OCB_OCCFLG_CLR;
extern uint32_t G_OCB_OCCFLG_OR;
extern uint32_t G_OCB_OCCFLG2;
extern uint32_t G_OCB_OCCFLG2_CLR;
extern uint32_t G_OCB_OCCS2;
extern uint32_t G_OCB_OISR0_CLR;
extern uint32_t G_OCB_OISR1;
Expand Down
2 changes: 2 additions & 0 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,8 @@ p9_sgpe_stop_entry()

if( in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ))
{
// Clear the injection so things are not permenently stuck
out32(G_OCB_OCCFLG2_CLR, BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ));
PK_TRACE_ERR("SGPE STOP ENTRY ERROR INJECT TRAP");
PK_PANIC(SGPE_STOP_ENTRY_TRAP_INJECT);
}
Expand Down
2 changes: 2 additions & 0 deletions import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -362,6 +362,8 @@ p9_sgpe_stop_exit()

if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ))
{
// Clear the injection so things are not permenently stuck
out32(G_OCB_OCCFLG2_CLR, BIT32(OCCFLG2_SGPE_HCODE_STOP_REQ_ERR_INJ));
PK_TRACE_ERR("SGPE STOP EXIT ERROR INJECT TRAP");
PK_PANIC(SGPE_STOP_EXIT_TRAP_INJECT);
}
Expand Down

0 comments on commit dc65a49

Please sign in to comment.