UV Support: CME Hcode changes to enable STOP entry exit in SMF mode.

Commit incorporates CME hcode changes that enable exit from STOP
as UV or HV at runtime.
Key_Cronus_Test=PM_REGRESS

Change-Id: Ia9ae0d284398af375f1562efff152a6a12a6eb9a
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64172
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h

@@ -101,6 +101,8 @@
 #define SPR_MODE               0x20010A84
 #define SCRATCH0               0x20010A86
 #define SCRATCH1               0x20010A87
+#define SCRATCH2               0x20010A88
+#define SCRATCH3               0x20010A89
 #define C_SPATTN_MASK          0x20010A9A
 #define THREAD_INFO            0x20010A9B
 #define DIRECT_CONTROLS        0x20010A9C

import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c

@@ -1181,6 +1181,31 @@ p9_cme_stop_exit()
 
 #endif
 
+            for (core_mask = 2; core_mask; core_mask--)
+            {
+                if (core & core_mask)
+                {
+                    CME_GETSCOM(CPPM_CPMMR, core_mask, scom_data.value);
+
+                    if (scom_data.words.upper & BIT32(3))
+                    {
+                        scom_data.value = BIT64(59);
+                    }
+                    else
+                    {
+                        scom_data.value = 0;
+                    }
+
+                    //Writing thread scratch register to
+                    // 1. Init Runtime wakeup mode for core.
+                    // 2. Signal Self Save Restore code for restore operation.
+                    CME_PUTSCOM(SCRATCH0, core_mask, scom_data.value);
+                    CME_PUTSCOM(SCRATCH1, core_mask, scom_data.value);
+                    CME_PUTSCOM(SCRATCH2, core_mask, scom_data.value);
+                    CME_PUTSCOM(SCRATCH3, core_mask, scom_data.value);
+                }
+            }
+
             PK_TRACE_PERF("SF.RS: Self Restore Kickoff, S-Reset All Core Threads");
 
             // Disable interrupts around the sreset to polling check to not miss the self-restore
@@ -1193,6 +1218,7 @@ p9_cme_stop_exit()
 
             while((~(in32_sh(CME_LCL_SISR))) & (core << SHIFT64SH(47)));
 
+
             wrteei(1);
 
             //==========================
@@ -1242,6 +1268,18 @@ p9_cme_stop_exit()
                 }
             }
 
+            for (core_mask = 2; core_mask; core_mask--)
+            {
+                if (core & core_mask)
+                {
+                    //Cleaning up thread scratch register after self restore.
+                    CME_PUTSCOM(SCRATCH0, core_mask, 0);
+                    CME_PUTSCOM(SCRATCH1, core_mask, 0);
+                    CME_PUTSCOM(SCRATCH2, core_mask, 0);
+                    CME_PUTSCOM(SCRATCH3, core_mask, 0);
+                }
+            }
+
             PK_TRACE_PERF("SF.RS: Self Restore Completed, Core Stopped Again(pm_exit=0/pm_active=1)");
 
             PK_TRACE("Restore SPATTN after self-restore");