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cmdh_fsp_cmds_datacnfg.c
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cmdh_fsp_cmds_datacnfg.c
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c $ */
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
#include "ssx.h"
#include "cmdh_service_codes.h"
#include "cmdh_fsp_cmds_datacnfg.h"
#include "errl.h"
#include "trac.h"
#include "rtls.h"
#include "dcom.h"
#include "occ_common.h"
#include "state.h"
#include "cmdh_fsp_cmds.h"
#include "cmdh_dbug_cmd.h"
#include "proc_pstate.h"
#include <amec_data.h>
#include "amec_amester.h"
#include "amec_service_codes.h"
#include "amec_sys.h"
#include <centaur_data.h>
#include "dimm.h"
#include "memory.h"
#include <avsbus.h>
#include "p9_pstates_occ.h"
#include <wof.h>
#include <i2c.h>
#define FREQ_FORMAT_PWR_MODE_NUM 6
#define FREQ_FORMAT_BASE_DATA_SZ (sizeof(cmdh_store_mode_freqs_t) - sizeof(cmdh_fsp_cmd_header_t))
#define FREQ_FORMAT_20_NUM_FREQS 6
#define DATA_FREQ_VERSION_20 0x20
#define DATA_PCAP_VERSION_20 0x20
#define DATA_SYS_VERSION_20 0x20
#define DATA_APSS_VERSION20 0x20
#define DATA_THRM_THRES_VERSION_20 0x20
#define THRM_THRES_BASE_DATA_SZ_20 5
#define DATA_IPS_VERSION 0
#define DATA_MEM_CFG_VERSION_20 0x20
#define DATA_MEM_CFG_VERSION_21 0x21
#define DATA_MEM_THROT_VERSION_20 0x20
extern uint8_t G_occ_interrupt_type;
extern uint16_t G_proc_fmax_mhz; // Maximum frequency (uturbo if WOF enabled, otherwise turbo)
extern OCCPstateParmBlock G_oppb; // OCC Pstate Parameters Block Structure
typedef struct data_req_table
{
uint32_t mask;
uint8_t format;
} data_req_table_t;
data_cnfg_t G_data_cnfg_static_obj = {0};
data_cnfg_t * G_data_cnfg = &G_data_cnfg_static_obj;
const data_req_table_t G_data_pri_table[] =
{
{DATA_MASK_SYS_CNFG, DATA_FORMAT_SYS_CNFG}, //Need this first so we can use correct huid's for callouts
{DATA_MASK_APSS_CONFIG, DATA_FORMAT_APSS_CONFIG}, //need apss config data prior to role data
{DATA_MASK_AVSBUS_CONFIG, DATA_FORMAT_AVSBUS_CONFIG},
{DATA_MASK_SET_ROLE, DATA_FORMAT_SET_ROLE},
{DATA_MASK_MEM_CFG, DATA_FORMAT_MEM_CFG},
{DATA_MASK_GPU, DATA_FORMAT_GPU},
{DATA_MASK_THRM_THRESHOLDS, DATA_FORMAT_THRM_THRESHOLDS},
{DATA_MASK_FREQ_PRESENT, DATA_FORMAT_FREQ},
{DATA_MASK_PCAP_PRESENT, DATA_FORMAT_POWER_CAP},
{DATA_MASK_MEM_THROT, DATA_FORMAT_MEM_THROT},
};
cmdh_ips_config_data_t G_ips_config_data = {0};
bool G_mem_monitoring_allowed = FALSE;
// Flag will get enabled when OCC receives Thermal Threshold data
bool G_vrm_thermal_monitoring = FALSE;
// Will get set when receiving APSS config data
PWR_READING_TYPE G_pwr_reading_type = PWR_READING_TYPE_NONE;
// Function Specification
//
// Name: DATA_get_present_cnfgdata
//
// Description: Accessor function for external access
//
// End Function Specification
uint32_t DATA_get_present_cnfgdata(void)
{
return G_data_cnfg->data_mask;
}
errlHndl_t DATA_get_thrm_thresholds(cmdh_thrm_thresholds_t **o_thrm_thresh)
{
errlHndl_t l_err = NULL;
if(G_data_cnfg->data_mask & DATA_MASK_THRM_THRESHOLDS)
{
*o_thrm_thresh = &(G_data_cnfg->thrm_thresh);
}
else
{
CMDH_TRAC_ERR("DATA_get_thrm_thresholds: Thermal Threshold data is unavailable! data_mask[0x%X]",
G_data_cnfg->data_mask);
/* @
* @errortype
* @moduleid DATA_GET_THRM_THRESHOLDS
* @reasoncode INTERNAL_FAILURE
* @userdata1 data mask showing which data OCC has received
* @userdata4 ERC_CMDH_THRM_DATA_MISSING
* @devdesc Someone is asking for the thermal control threholds
* and OCC hasn't received them yet from the FSP!
*/
l_err = createErrl(DATA_GET_THRM_THRESHOLDS,
INTERNAL_FAILURE,
ERC_CMDH_THRM_DATA_MISSING,
ERRL_SEV_PREDICTIVE,
NULL,
DEFAULT_TRACE_SIZE,
G_data_cnfg->data_mask,
0);
}
return l_err;
}
errlHndl_t DATA_get_ips_cnfg(cmdh_ips_config_data_t **o_ips_cnfg)
{
errlHndl_t l_err = NULL;
if(G_data_cnfg->data_mask & DATA_MASK_IPS_CNFG)
{
*o_ips_cnfg = &G_ips_config_data;
}
else
{
CMDH_TRAC_ERR("DATA_get_ips_cnfg: IPS Config data is unavailable! data_mask[0x%X]",
G_data_cnfg->data_mask);
/* @
* @errortype
* @moduleid DATA_GET_IPS_DATA
* @reasoncode INTERNAL_FAILURE
* @userdata1 data mask showing which data OCC has received
* @userdata4 ERC_CMDH_IPS_DATA_MISSING
* @devdesc Someone is asking for the Idle Power Save config data
* and OCC hasn't received them yet from the FSP!
*/
l_err = createErrl(DATA_GET_IPS_DATA,
INTERNAL_FAILURE,
ERC_CMDH_IPS_DATA_MISSING,
ERRL_SEV_PREDICTIVE,
NULL,
DEFAULT_TRACE_SIZE,
G_data_cnfg->data_mask,
0);
}
return l_err;
}
// Function Specification
//
// Name: DATA_request_cnfgdata
//
// Description: Determine what config data should be requested from TMGT
//
// End Function Specification
uint8_t DATA_request_cnfgdata ()
{
uint8_t l_req = 0x00; // Data to request
uint16_t i = 0;
uint16_t l_array_size = 0;
l_array_size = sizeof(G_data_pri_table) / sizeof(data_req_table_t);
for(i=0;i<l_array_size;i++)
{
// Skip requesting memory throttle values if memory monitoring
// is not being allowed by TMGT.
if((G_data_pri_table[i].format == DATA_FORMAT_MEM_THROT) &&
!G_mem_monitoring_allowed)
{
continue;
}
// Skip whenever we are trying to request pcap or freq as a slave
if(((G_data_pri_table[i].format == DATA_FORMAT_POWER_CAP) ||
(G_data_pri_table[i].format == DATA_FORMAT_FREQ)) &&
(G_occ_role == OCC_SLAVE))
{
continue;
}
// Go through priority table and request first data found which has
// not been provided
if(!(G_data_cnfg->data_mask & G_data_pri_table[i].mask))
{
l_req = G_data_pri_table[i].format;
break;
}
}
return(l_req);
}
// Function Specification
//
// Name: data_store_freq_data
//
// Description: Write all of the frequency points from TMGT into G_sysConfigData
//
// End Function Specification
errlHndl_t data_store_freq_data(const cmdh_fsp_cmd_t * i_cmd_ptr,
cmdh_fsp_rsp_t * o_rsp_ptr)
{
errlHndl_t l_err = NULL;
cmdh_store_mode_freqs_t* l_cmdp = (cmdh_store_mode_freqs_t*)i_cmd_ptr;
uint8_t* l_buf = ((uint8_t*)(l_cmdp)) + sizeof(cmdh_store_mode_freqs_t);
uint16_t l_data_length;
uint32_t l_mode_data_sz;
uint16_t l_freq = 0;
uint8_t l_count = FREQ_FORMAT_PWR_MODE_NUM;
uint16_t l_table[OCC_MODE_COUNT] = {0};
do
{
l_data_length = CMDH_DATALEN_FIELD_UINT16(l_cmdp);
l_mode_data_sz = l_data_length - FREQ_FORMAT_BASE_DATA_SZ;
// Sanity Checks
// If the datapacket is bigger than what we can store, OR
// if the version doesn't equal what we expect, OR
// if the expected data length does not agree with the actual data length
if((l_data_length < FREQ_FORMAT_BASE_DATA_SZ) ||
(l_cmdp->version != DATA_FREQ_VERSION_20) ||
((DATA_FREQ_VERSION_20 == l_cmdp->version) && (l_mode_data_sz != (FREQ_FORMAT_20_NUM_FREQS * 2))))
{
CMDH_TRAC_ERR("Invalid Frequency Data packet: data_length[%u] version[%u] l_count[%u] l_mode_data_sz[%u]",
l_data_length, l_cmdp->version, l_count, l_mode_data_sz);
cmdh_build_errl_rsp(i_cmd_ptr, o_rsp_ptr, ERRL_RC_INVALID_DATA, &l_err);
break;
}
if(OCC_MASTER != G_occ_role)
{
// We want to ignore this cnfg data if we are not the master.
CMDH_TRAC_INFO("Received a Frequncy Data Packet on a Slave OCC: Ignore!");
break;
}
if(DATA_FREQ_VERSION_20 == l_cmdp->version) // Version 0x20
{
// 1) Nominal, 2) Turbo, 3) Minimum,
// 4) Ultra Turbo, 5) Static PS, 6) FFO
// store under the existing enums.
// Bytes 3-4 Nominal Frequency Point
l_freq = (l_buf[0] << 8 | l_buf[1]);
l_table[OCC_MODE_NOMINAL] = l_freq;
CMDH_TRAC_INFO("Nominal frequency = %d MHz", l_freq);
// Bytes 5-6 Turbo Frequency Point:
// also store for DPS modes
l_freq = (l_buf[2] << 8 | l_buf[3]);
// Verify that turbo frequency is <= G_proc_fmax_mhz
if(l_freq > G_proc_fmax_mhz)
{
CMDH_TRAC_ERR("Turbo Frequency[%d] (MHz)) is higher than "
"G_proc_fmax_mhz[%d], clip Turbo Frequency",
l_freq, G_proc_fmax_mhz);
l_freq = G_proc_fmax_mhz;
}
l_table[OCC_MODE_TURBO] = l_freq;
CMDH_TRAC_INFO("Turbo frequency = %d MHz", l_freq);
// Bytes 7-8 Minimum Frequency Point
l_freq = (l_buf[4] << 8 | l_buf[5]);
// Verify that minimum frequency is >= G_oppb.frequency_min_khz
if(l_freq * 1000 < G_oppb.frequency_min_khz)
{
CMDH_TRAC_ERR("Minimum Frequency[%d] (Mhz) is lower than PGPE's "
"G_oppb.frequency_min_khz[%d], clip Minimum Frequency",
l_freq, G_oppb.frequency_min_khz);
l_freq = G_oppb.frequency_min_khz / 1000;
}
l_table[OCC_MODE_MIN_FREQUENCY] = l_freq;
CMDH_TRAC_INFO("Minimum frequency = %d MHz", l_freq);
// Bytes 9-10 Ultr Turbo Frequency Point
l_freq = (l_buf[6] << 8 | l_buf[7]);
// Verify that ultra turbo frequency is <= G_proc_fmax_mhz
if(l_freq > G_proc_fmax_mhz)
{
CMDH_TRAC_ERR("Ultra Turbo Frequency[%d] (MHz) is higher than PGPE's "
"Max freq (G_proc_fmax_mhz[%d]) clip Ultra Turbo Frequency",
l_freq, G_proc_fmax_mhz);
l_freq = G_proc_fmax_mhz;
}
// Check if (H)TMGT will let WOF run, else clear flags
switch( l_freq )
{
case WOF_MISSING_ULTRA_TURBO:
CMDH_TRAC_INFO("WOF Disabled due to 0 UT value.");
set_clear_wof_disabled( SET, WOF_RC_UTURBO_IS_ZERO );
l_freq = 0;
break;
case WOF_SYSTEM_DISABLED:
CMDH_TRAC_INFO("WOF Disabled due to SYSTEM_WOF_DISABLE");
set_clear_wof_disabled( SET, WOF_RC_SYSTEM_WOF_DISABLE );
l_freq = 0;
break;
case WOF_RESET_LIMIT_REACHED:
CMDH_TRAC_INFO("WOF Disabled due to reset limit");
set_clear_wof_disabled( SET, WOF_RC_RESET_LIMIT_REACHED );
l_freq = 0;
break;
case WOF_UNSUPPORTED_FREQ:
CMDH_TRAC_INFO("WOF Disabled due to unsupported frequency");
set_clear_wof_disabled( SET, WOF_RC_UNSUPPORTED_FREQUENCIES );
l_freq = 0;
break;
default:
CMDH_TRAC_INFO("WOF is Enabled! so far...");
set_clear_wof_disabled( CLEAR, WOF_RC_UTURBO_IS_ZERO );
set_clear_wof_disabled( CLEAR, WOF_RC_SYSTEM_WOF_DISABLE );
set_clear_wof_disabled( CLEAR, WOF_RC_RESET_LIMIT_REACHED );
set_clear_wof_disabled( CLEAR, WOF_RC_UNSUPPORTED_FREQUENCIES );
set_clear_wof_disabled( CLEAR, WOF_RC_OCC_WOF_DISABLED );
break;
}
l_table[OCC_MODE_UTURBO] = l_freq;
CMDH_TRAC_INFO("UT frequency = %d MHz", l_freq);
// clip G_proc_fmax_mhz to TMGT's MAX(turbo, ultra turbo) frequency point
if(l_table[OCC_MODE_UTURBO] > l_table[OCC_MODE_TURBO])
{
G_proc_fmax_mhz = l_table[OCC_MODE_UTURBO];
}
else
{
G_proc_fmax_mhz = l_table[OCC_MODE_TURBO];
}
// Set dynamic power save frequencies
l_table[OCC_MODE_DYN_POWER_SAVE] = G_proc_fmax_mhz;
l_table[OCC_MODE_DYN_POWER_SAVE_FP] = G_proc_fmax_mhz;
// Bytes 11-12 Static Power Save Frequency Point
l_freq = (l_buf[8] << 8 | l_buf[9]);
// in case min freq was clipped verify power save not below min
if(l_freq < l_table[OCC_MODE_MIN_FREQUENCY])
{
CMDH_TRAC_ERR("Power Save Frequency[%d] is lower than min[%d]",
l_freq, l_table[OCC_MODE_MIN_FREQUENCY]);
l_freq = l_table[OCC_MODE_MIN_FREQUENCY];
}
l_table[OCC_MODE_PWRSAVE] = l_freq;
CMDH_TRAC_INFO("Static Power Save frequency = %d MHz", l_freq);
// Bytes 13-14 FFO Frequency Point
l_freq = (l_buf[10] << 8 | l_buf[11]);
if (l_freq != 0)
{
// Check and make sure that FFO freq is within valid range
const uint16_t l_req_freq = l_freq;
if (l_freq < l_table[OCC_MODE_MIN_FREQUENCY])
{
l_freq = l_table[OCC_MODE_MIN_FREQUENCY];
}
else if (l_freq > G_proc_fmax_mhz)
{
l_freq = G_proc_fmax_mhz;
}
// Log an error if we could not honor the requested FFO frequency, but keep going.
if (l_req_freq != l_freq)
{
TRAC_ERR("FFO Frequency out of range. requested %d MHz, but using %d MHz",
l_req_freq, l_freq);
/* @
* @errortype
* @moduleid DATA_STORE_FREQ_DATA
* @reasoncode INVALID_INPUT_DATA
* @userdata1 requested frequency
* @userdata2 frequency used
* @userdata4 OCC_NO_EXTENDED_RC
* @devdesc OCC recieved an invalid FFO frequency
*/
l_err = createErrl(DATA_STORE_FREQ_DATA,
INVALID_INPUT_DATA,
OCC_NO_EXTENDED_RC,
ERRL_SEV_INFORMATIONAL,
NULL,
DEFAULT_TRACE_SIZE,
l_req_freq,
l_freq);
commitErrl(&l_err);
}
}
}
l_table[OCC_MODE_FFO] = l_freq;
CMDH_TRAC_INFO("FFO Frequency = %d Mhz", l_freq);
// inconsistent Frequency Points?
if((l_table[OCC_MODE_UTURBO] < l_table[OCC_MODE_TURBO] && l_table[OCC_MODE_UTURBO]) ||
l_table[OCC_MODE_TURBO] < l_table[OCC_MODE_NOMINAL] ||
l_table[OCC_MODE_NOMINAL] < l_table[OCC_MODE_PWRSAVE] ||
l_table[OCC_MODE_PWRSAVE] < l_table[OCC_MODE_MIN_FREQUENCY])
{
CMDH_TRAC_ERR("Inconsistent Frequency points - UT-T=0x%x, NOM-PS=0x%x, MIN=0x%x",
(l_table[OCC_MODE_UTURBO] << 16) + l_table[OCC_MODE_TURBO],
(l_table[OCC_MODE_NOMINAL] << 16) + l_table[OCC_MODE_PWRSAVE],
l_table[OCC_MODE_MIN_FREQUENCY]);
}
}while(0);
// Change Data Request Mask to indicate we got this data
if(!l_err && (G_occ_role == OCC_MASTER))
{
// Copy all of the frequency updates to the global and notify
// dcom of the new frequenies.
memcpy(G_sysConfigData.sys_mode_freq.table, l_table, sizeof(l_table));
G_sysConfigData.sys_mode_freq.update_count++;
G_data_cnfg->data_mask |= DATA_MASK_FREQ_PRESENT;
}
return l_err;
}
// Function Specification
//
// Name: apss_store_adc_channel
//
// Description: Matches the functional ID (from MRW) to the APSS ADC channel
//
// End Function Specification
errlHndl_t apss_store_adc_channel(const eApssAdcChannelAssignments i_func_id, const uint8_t i_channel_num )
{
errlHndl_t l_err = NULL;
// Check function ID and channel number
if ( (i_func_id >= NUM_ADC_ASSIGNMENT_TYPES) ||
(i_channel_num >= MAX_APSS_ADC_CHANNELS) )
{
CMDH_TRAC_ERR("apss_store_adc_channel: Invalid function ID or channel number (id:0x%x, channel:%d)", i_func_id, i_channel_num);
/* @
* @errortype
* @moduleid DATA_STORE_APSS_DATA
* @reasoncode INVALID_INPUT_DATA
* @userdata1 function ID
* @userdata2 channel number
* @userdata4 ERC_APSS_ADC_OUT_OF_RANGE_FAILURE
* @devdesc Invalid function ID or channel number
*/
l_err = createErrl(DATA_STORE_APSS_DATA,
INVALID_INPUT_DATA,
ERC_APSS_ADC_OUT_OF_RANGE_FAILURE,
ERRL_SEV_UNRECOVERABLE,
NULL,
DEFAULT_TRACE_SIZE,
(uint32_t)i_func_id,
(uint32_t)i_channel_num);
// Callout firmware
addCalloutToErrl(l_err,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
}
else
{
uint8_t *l_adc_function=NULL;
switch (i_func_id)
{
case ADC_RESERVED:
// Do nothing
break;
case ADC_MEMORY_PROC_0:
case ADC_MEMORY_PROC_1:
case ADC_MEMORY_PROC_2:
case ADC_MEMORY_PROC_3:
l_adc_function = &G_sysConfigData.apss_adc_map.memory[i_func_id-ADC_MEMORY_PROC_0][0];
break;
case ADC_MEMORY_PROC_0_0:
l_adc_function = &G_sysConfigData.apss_adc_map.memory[0][1];
break;
case ADC_MEMORY_PROC_0_1:
l_adc_function = &G_sysConfigData.apss_adc_map.memory[0][2];
break;
case ADC_MEMORY_PROC_0_2:
l_adc_function = &G_sysConfigData.apss_adc_map.memory[0][3];
break;
case ADC_VDD_PROC_0:
case ADC_VDD_PROC_1:
case ADC_VDD_PROC_2:
case ADC_VDD_PROC_3:
l_adc_function = &G_sysConfigData.apss_adc_map.vdd[i_func_id-ADC_VDD_PROC_0];
break;
case ADC_VCS_VIO_VPCIE_PROC_0:
case ADC_VCS_VIO_VPCIE_PROC_1:
case ADC_VCS_VIO_VPCIE_PROC_2:
case ADC_VCS_VIO_VPCIE_PROC_3:
l_adc_function = &G_sysConfigData.apss_adc_map.vcs_vio_vpcie[i_func_id-ADC_VCS_VIO_VPCIE_PROC_0];
break;
case ADC_IO_A:
case ADC_IO_B:
case ADC_IO_C:
l_adc_function = &G_sysConfigData.apss_adc_map.io[i_func_id-ADC_IO_A];
break;
case ADC_FANS_A:
case ADC_FANS_B:
l_adc_function = &G_sysConfigData.apss_adc_map.fans[i_func_id-ADC_FANS_A];
break;
case ADC_STORAGE_A:
case ADC_STORAGE_B:
l_adc_function = &G_sysConfigData.apss_adc_map.storage_media[i_func_id-ADC_STORAGE_A];
break;
case ADC_12V_SENSE:
l_adc_function = &G_sysConfigData.apss_adc_map.sense_12v;
break;
case ADC_GND_REMOTE_SENSE:
l_adc_function = &G_sysConfigData.apss_adc_map.remote_gnd;
break;
case ADC_TOTAL_SYS_CURRENT:
l_adc_function = &G_sysConfigData.apss_adc_map.total_current_12v;
break;
case ADC_MEM_CACHE:
l_adc_function = &G_sysConfigData.apss_adc_map.mem_cache;
break;
case ADC_12V_STANDBY_CURRENT:
l_adc_function = &G_sysConfigData.apss_adc_map.current_12v_stby;
break;
case ADC_GPU_0_0:
l_adc_function = &G_sysConfigData.apss_adc_map.gpu[0][0];
break;
case ADC_GPU_0_1:
l_adc_function = &G_sysConfigData.apss_adc_map.gpu[0][1];
break;
case ADC_GPU_0_2:
l_adc_function = &G_sysConfigData.apss_adc_map.gpu[0][2];
break;
case ADC_GPU_1_0:
l_adc_function = &G_sysConfigData.apss_adc_map.gpu[1][0];
break;
case ADC_GPU_1_1:
l_adc_function = &G_sysConfigData.apss_adc_map.gpu[1][1];
break;
case ADC_GPU_1_2:
l_adc_function = &G_sysConfigData.apss_adc_map.gpu[1][2];
break;
default:
// It should never happen
CMDH_TRAC_ERR("apss_store_adc_channel: Invalid function ID: 0x%x", i_func_id);
break;
}
if(NULL != l_adc_function)
{
// Check if this function already have ADC channel assigned
if( SYSCFG_INVALID_ADC_CHAN == *l_adc_function)
{
*l_adc_function = i_channel_num;
G_apss_ch_to_function[i_channel_num] = i_func_id;
CNFG_DBG("apss_store_adc_channel: func_id[0x%02X] stored as 0x%02X for channel %d",
i_func_id, G_apss_ch_to_function[i_channel_num], *l_adc_function);
}
else
{
CMDH_TRAC_ERR("apss_store_adc_channel: Function ID is duplicated (id:0x%x, channel:%d)", i_func_id, i_channel_num);
/* @
* @errortype
* @moduleid DATA_STORE_APSS_DATA
* @reasoncode INVALID_INPUT_DATA
* @userdata1 function ID
* @userdata2 channel number
* @userdata4 ERC_APSS_ADC_DUPLICATED_FAILURE
* @devdesc Function ID is duplicated
*/
l_err = createErrl(DATA_STORE_APSS_DATA,
INVALID_INPUT_DATA,
ERC_APSS_ADC_DUPLICATED_FAILURE,
ERRL_SEV_UNRECOVERABLE,
NULL,
DEFAULT_TRACE_SIZE,
(uint32_t)i_func_id,
(uint32_t)i_channel_num);
// Callout firmware
addCalloutToErrl(l_err,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
}
}
}
return l_err;
}
// Function Specification
//
// Name: apss_store_ipmi_sensor_id
//
// Description: Writes the given ipmi sensor ID provided by tmgt to the
// associated power sensor.
//
// End Function Specification
void apss_store_ipmi_sensor_id(const uint16_t i_channel, const apss_cfg_adc_v20_t *i_adc)
{
// Get current processor id.
uint8_t l_proc = G_pbax_id.chip_id;
switch (i_adc->assignment)
{
case ADC_RESERVED:
// Do nothing; given channel is not utilized.
break;
case ADC_MEMORY_PROC_0:
case ADC_MEMORY_PROC_1:
case ADC_MEMORY_PROC_2:
case ADC_MEMORY_PROC_3:
if (l_proc == (i_adc->assignment - ADC_MEMORY_PROC_0))
{
AMECSENSOR_PTR(PWRMEM)->ipmi_sid = i_adc->ipmisensorId;
}
break;
case ADC_IO_A:
case ADC_IO_B:
case ADC_IO_C:
if (i_adc->ipmisensorId != 0)
{
AMECSENSOR_PTR(PWRIO)->ipmi_sid = i_adc->ipmisensorId;
}
break;
case ADC_FANS_A:
case ADC_FANS_B:
if (i_adc->ipmisensorId != 0)
{
AMECSENSOR_PTR(PWRFAN)->ipmi_sid = i_adc->ipmisensorId;
}
break;
case ADC_STORAGE_A:
case ADC_STORAGE_B:
if (i_adc->ipmisensorId != 0)
{
AMECSENSOR_PTR(PWRSTORE)->ipmi_sid = i_adc->ipmisensorId;
}
break;
case ADC_12V_SENSE:
//None
break;
case ADC_GND_REMOTE_SENSE:
//None
break;
case ADC_TOTAL_SYS_CURRENT:
//None
break;
case ADC_MEM_CACHE:
//None
break;
case ADC_12V_STANDBY_CURRENT:
//None
break;
case ADC_GPU_0_0:
case ADC_GPU_0_1:
case ADC_GPU_0_2:
if((i_adc->ipmisensorId != 0) && (l_proc == 0))
{
AMECSENSOR_PTR(PWRGPU)->ipmi_sid = i_adc->ipmisensorId;
}
break;
case ADC_GPU_1_0:
case ADC_GPU_1_1:
case ADC_GPU_1_2:
if((i_adc->ipmisensorId != 0) && (l_proc == 1))
{
AMECSENSOR_PTR(PWRGPU)->ipmi_sid = i_adc->ipmisensorId;
}
break;
default:
break;
}
//Write sensor ID to channel sensors. If the assignment(function id) is 0, that means
//the channel is not being utilized.
if ((i_channel < MAX_APSS_ADC_CHANNELS) && (i_adc->assignment != ADC_RESERVED))
{
if ((i_adc->ipmisensorId == 0) && (G_occ_interrupt_type != FSP_SUPPORTED_OCC))
{
// Sensor IDs are not required and only used for BMC based systems
CMDH_TRAC_INFO("apss_store_ipmi_sensor_id: No Sensor ID for channel %i.",i_channel);
//We need to generate a generic sensor ID if we want channels with functionIDs but
//no sensor IDs to be reported in the poll command.
}
//Only store sensor ids for power sensors. 12V sensor and gnd remote sensors do not report power used.
if ((i_adc->assignment != ADC_12V_SENSE) && (i_adc->assignment != ADC_GND_REMOTE_SENSE) &&
(i_adc->assignment != ADC_12V_STANDBY_CURRENT))
{
AMECSENSOR_PTR(PWRAPSSCH0 + i_channel)->ipmi_sid = i_adc->ipmisensorId;
CNFG_DBG("apss_store_ipmi_sensor_id: SID[0x%08X] stored as 0x%08X for channel %d",
i_adc->ipmisensorId, AMECSENSOR_PTR(PWRAPSSCH0 + i_channel)->ipmi_sid, i_channel);
}
}
}
// Function Specification
//
// Name: apss_store_gpio_pin
//
// Description: Matches the functional ID (from MRW) to the APSS GPIO pin
//
// End Function Specification
errlHndl_t apss_store_gpio_pin(const eApssGpioAssignments i_func_id, const uint8_t i_gpio_num )
{
errlHndl_t l_err = NULL;
// Check function ID and channel number
if ( (i_func_id >= NUM_GPIO_ASSIGNMENT_TYPES) ||
( i_gpio_num >= (MAX_APSS_GPIO_PORTS*NUM_OF_APSS_PINS_PER_GPIO_PORT) ) )
{
CMDH_TRAC_ERR("apss_store_gpio_pin: Invalid function ID or gpio number (id:0x%x, pin:%d)", i_func_id, i_gpio_num);
/* @
* @errortype
* @moduleid DATA_STORE_APSS_DATA
* @reasoncode INVALID_INPUT_DATA
* @userdata1 function ID
* @userdata2 gpio number
* @userdata4 ERC_APSS_GPIO_OUT_OF_RANGE_FAILURE
* @devdesc Invalid function ID or gpio number
*/
l_err = createErrl(DATA_STORE_APSS_DATA,
INVALID_INPUT_DATA,
ERC_APSS_GPIO_OUT_OF_RANGE_FAILURE,
ERRL_SEV_UNRECOVERABLE,
NULL,
DEFAULT_TRACE_SIZE,
(uint32_t)i_func_id,
(uint32_t)i_gpio_num);
// Callout firmware
addCalloutToErrl(l_err,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
}
else
{
uint8_t *l_gpio_function = NULL;
switch (i_func_id)
{
case GPIO_RESERVED:
// Do nothing
break;
case GPIO_FAN_WATCHDOG_ERROR:
l_gpio_function = &G_sysConfigData.apss_gpio_map.fans_watchdog_error;
break;
case GPIO_FAN_FULL_SPEED:
l_gpio_function = &G_sysConfigData.apss_gpio_map.fans_full_speed;
break;
case GPIO_FAN_ERROR:
l_gpio_function = &G_sysConfigData.apss_gpio_map.fans_error;
break;
case GPIO_FAN_RESERVED:
l_gpio_function = &G_sysConfigData.apss_gpio_map.fans_reserved;
break;
case GPIO_VR_HOT_MEM_PROC_0:
case GPIO_VR_HOT_MEM_PROC_1:
case GPIO_VR_HOT_MEM_PROC_2:
case GPIO_VR_HOT_MEM_PROC_3:
l_gpio_function = &G_sysConfigData.apss_gpio_map.vr_fan[i_func_id-GPIO_VR_HOT_MEM_PROC_0];
break;
case GPIO_CENT_EN_VCACHE0:
case GPIO_CENT_EN_VCACHE1:
case GPIO_CENT_EN_VCACHE2:
case GPIO_CENT_EN_VCACHE3:
l_gpio_function = &G_sysConfigData.apss_gpio_map.cent_en_vcache[i_func_id-GPIO_CENT_EN_VCACHE0];
break;
case CME_THROTTLE_N:
l_gpio_function = &G_sysConfigData.apss_gpio_map.cme_throttle_n;
break;
case GND_OC_N:
l_gpio_function = &G_sysConfigData.apss_gpio_map.gnd_oc_n;
break;
case DOM_A_OC_LATCH:
case DOM_B_OC_LATCH:
case DOM_C_OC_LATCH:
case DOM_D_OC_LATCH:
l_gpio_function = &G_sysConfigData.apss_gpio_map.dom_oc_latch[i_func_id-DOM_A_OC_LATCH];
break;
case PSU_FAN_DISABLE_N:
l_gpio_function = &G_sysConfigData.apss_gpio_map.psu_fan_disable;
break;
case GPU_0_0_PRSNT_N:
case GPU_0_1_PRSNT_N:
case GPU_0_2_PRSNT_N:
case GPU_1_0_PRSNT_N:
case GPU_1_1_PRSNT_N:
case GPU_1_2_PRSNT_N:
l_gpio_function = &G_sysConfigData.apss_gpio_map.gpu[i_func_id-GPU_0_0_PRSNT_N];
break;
case NVDIMM_EPOW_N:
l_gpio_function = &G_sysConfigData.apss_gpio_map.nvdimm_epow;
break;
default:
// It should never happen
CMDH_TRAC_ERR("apss_store_gpio_pin: Invalid function ID: 0x%x", i_func_id);
break;
}
if(NULL != l_gpio_function)
{
// Check if this function already have ADC channel assigned
if( SYSCFG_INVALID_PIN == *l_gpio_function)
{
*l_gpio_function = i_gpio_num;
CNFG_DBG("apss_store_gpio_pin: func_id[0x%02X] is mapped to pin 0x%02X", i_func_id, *l_gpio_function);
}
else
{
CMDH_TRAC_ERR("apss_store_gpio_pin: Function ID is duplicated (id:0x%x, pin:%d)", i_func_id, i_gpio_num);
/* @
* @errortype
* @moduleid DATA_STORE_APSS_DATA
* @reasoncode INVALID_INPUT_DATA
* @userdata1 function ID
* @userdata2 gpio number
* @userdata4 ERC_APSS_GPIO_DUPLICATED_FAILURE
* @devdesc Invalid function ID or channel number
*/
l_err = createErrl(DATA_STORE_APSS_DATA,
INVALID_INPUT_DATA,
ERC_APSS_GPIO_DUPLICATED_FAILURE,
ERRL_SEV_UNRECOVERABLE,
NULL,
DEFAULT_TRACE_SIZE,
(uint32_t)i_func_id,
(uint32_t)i_gpio_num);
// Callout firmware
addCalloutToErrl(l_err,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);
}
}
}
return l_err;
}
// Function Specification
//
// Name: data_store_apss_config_v20
//
// Description: Configuration required for APSS
//
// End Function Specification
errlHndl_t data_store_apss_config_v20(const cmdh_apss_config_v20_t * i_cmd_ptr,
cmdh_fsp_rsp_t * o_rsp_ptr)
{
errlHndl_t l_err = NULL;
uint16_t l_channel = 0, l_port = 0, l_pin = 0, l_num_channels = MAX_APSS_ADC_CHANNELS;
// ADC channels info
if(G_pwr_reading_type == PWR_READING_TYPE_2_CHANNEL)
l_num_channels = 2;
else
{
// This must be APSS type, however it is possible that xml and/or HTMGT doesn't support
// indication of no APSS so we will default to none and then set to APSS if valid channel found
G_pwr_reading_type = PWR_READING_TYPE_NONE;
}
for(l_channel=0;(l_channel < l_num_channels) && (NULL == l_err);l_channel++)
{
G_sysConfigData.apss_cal[l_channel].gnd_select = i_cmd_ptr->adc[l_channel].gnd_select;
G_sysConfigData.apss_cal[l_channel].gain = i_cmd_ptr->adc[l_channel].gain;
G_sysConfigData.apss_cal[l_channel].offset = i_cmd_ptr->adc[l_channel].offset;
// Assign the ADC channels
l_err = apss_store_adc_channel(i_cmd_ptr->adc[l_channel].assignment, l_channel);
if (l_err == NULL)
{
//Write sensor IDs to the appropriate powr sensors.
apss_store_ipmi_sensor_id(l_channel, &(i_cmd_ptr->adc[l_channel]));
// APSS is present if there is at least one channel with a valid assignment
if( (i_cmd_ptr->adc[l_channel].assignment != ADC_RESERVED) &&
(G_pwr_reading_type == PWR_READING_TYPE_NONE) )
{
G_pwr_reading_type = PWR_READING_TYPE_APSS;
}
}
CNFG_DBG("data_store_apss_config_v20: Channel %d: FuncID[0x%02X] SID[0x%08X]",
l_channel, i_cmd_ptr->adc[l_channel].assignment, i_cmd_ptr->adc[l_channel].ipmisensorId);
CNFG_DBG("data_store_apss_config_v20: Channel %d: GND[0x%02X] Gain[0x%08X] Offst[0x%08X]",
l_channel, G_sysConfigData.apss_cal[l_channel].gnd_select, G_sysConfigData.apss_cal[l_channel].gain,
G_sysConfigData.apss_cal[l_channel].offset);
}
if( (NULL == l_err) && (G_pwr_reading_type == PWR_READING_TYPE_APSS) ) // only APSS has GPIO config
{
// GPIO Ports
for(l_port=0;(l_port < MAX_APSS_GPIO_PORTS) && (NULL == l_err);l_port++)
{
// GPIO mode
G_sysConfigData.apssGpioPortsMode[l_port] = i_cmd_ptr->gpio[l_port].mode;
// For each pin