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wof.c
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wof.c
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/occ_405/wof/wof.c $ */
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
#include <errl.h>
#include <trac.h>
#include <sensor.h>
#include <occhw_async.h>
#include <pgpe_shared.h>
#include <pstate_pgpe_occ_api.h>
#include <p9_pstates_occ.h>
#include <occ_service_codes.h>
#include <wof_service_codes.h>
#include <amec_sys.h>
#include <occ_sys_config.h>
#include <wof.h>
#include <amec_freq.h>
#include <pgpe_interface.h>
#include <avsbus.h>
#include "common.h" // For ignore_pgpe_error()
//******************************************************************************
// External Globals
//******************************************************************************
extern amec_sys_t g_amec_sys;
extern OCCPstateParmBlock G_oppb;
extern GPE_BUFFER(ipcmsg_wof_vfrt_t G_wof_vfrt_parms);
extern GPE_BUFFER(ipcmsg_wof_control_t G_wof_control_parms);
extern GpeRequest G_wof_vfrt_req;
extern GpeRequest G_wof_control_req;
extern uint32_t G_nest_frequency_mhz;
extern volatile pstateStatus G_proc_pstate_status;
extern uint8_t G_occ_interrupt_type;
extern bool G_pgpe_shared_sram_V_I_readings;
extern uint16_t G_allow_trace_flags;
//******************************************************************************
// Globals
//******************************************************************************
uint8_t G_sram_vfrt_ping_buffer[MIN_BCE_REQ_SIZE] __attribute__ ((section(".vfrt_ping_buffer")));
uint8_t G_sram_vfrt_pong_buffer[MIN_BCE_REQ_SIZE] __attribute__ ((section(".vfrt_pong_buffer")));
// BCE Request object for retrieving VFRT's from Mainstore
BceRequest G_vfrt_req;
// Buffer to hold vfrt from main memory
DMA_BUFFER(temp_bce_request_buffer_t G_vfrt_temp_buff) = {{0}};
// Wof header struct
wof_header_data_t G_wof_header __attribute__ ((section (".global_data")));
// Quad state structs to temporarily hold the data from the doublewords to
// then populate in amec structure
quad_state0_t G_quad_state_0 = {0};
quad_state1_t G_quad_state_1 = {0};
// Create a pointer to amec WOF structure
amec_wof_t * g_wof = &(g_amec_sys.wof);
// Core IDDQ voltages array (voltages in 100uV)
uint16_t G_iddq_voltages[CORE_IDDQ_MEASUREMENTS] =
{
6000,
7000,
8000,
9000,
10000,
11000
};
// Approximate y = full_leakage_08V^(-((T-tvpd_leak)/257.731))*1.45^((T-tvpd_leak)/10)
// full_leakage_08V is not data we have, it is a ALL core,cache,quad ON leakage measure they do at MFT.
// We can estimate by using the IQ data at 0.8v * 24/#sort cores
// Interpolate (T-tvpd_leak) for full leakage 0.8V in the table below to find m.
// y ~= (T*m) >> 10 (shift out 10 bits)
// Error in estimation is no more than 0.9%
// The first column represents the result of T-tvpd_leak where T is the
// associated temperature sensor.
// The second column represents the associated m(slope) with the delta temp (first column)
#define NUM_FULL_LEAKAGE_08V 10
#define WOF_IDDQ_MULT_TABLE_N 21
uint32_t G_wof_mft_full_leakage_08V[WOF_IDDQ_MULT_TABLE_N + 1][NUM_FULL_LEAKAGE_08V] = {
// First row is header of voltage values in mA remaining rows are m values
// for the full leakage @0.8V for each temperature in first column of G_wof_iddq_mult_table
// this table is used for one time interpolation to create the final m values in
// G_wof_iddq_mult_table (the temperatures are not repeated in this table)
{20000, 30000, 40000, 50000, 60000, 70000, 80000, 90000, 100000, 110000}, // header in mA
{ 171, 191, 207, 220, 231, 241, 250, 258, 265, 272}, // -70 temp delta
{ 195, 216, 232, 245, 257, 267, 276, 285, 292, 299}, // -65 temp delta
{ 221, 243, 260, 274, 286, 296, 306, 314, 322, 329}, // -60 temp delta
{ 251, 274, 292, 306, 318, 328, 338, 347, 354, 362}, // -55 temp delta
{ 286, 309, 327, 341, 354, 364, 374, 382, 390, 398}, // -50 temp delta
{ 325, 348, 366, 381, 393, 404, 413, 422, 430, 437}, // -45 temp delta
{ 369, 393, 411, 425, 437, 448, 457, 466, 473, 480}, // -40 temp delta
{ 419, 443, 460, 474, 486, 497, 506, 514, 521, 528}, // -35 temp delta
{ 476, 499, 516, 530, 541, 551, 559, 567, 574, 581}, // -30 temp delta
{ 541, 563, 578, 591, 602, 611, 619, 626, 632, 638}, // -25 temp delta
{ 615, 634, 648, 660, 669, 677, 684, 691, 696, 701}, // -20 temp delta
{ 698, 715, 727, 736, 744, 751, 757, 762, 767, 771}, // -15 temp delta
{ 793, 806, 815, 822, 828, 833, 837, 841, 844, 847}, // -10 temp delta
{ 901, 908, 913, 917, 921, 923, 926, 928, 930, 932}, // -5 temp delta
{ 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024}, // 0 temp delta
{ 1163, 1154, 1148, 1143, 1139, 1136, 1133, 1130, 1128, 1126}, // 5 temp delta
{ 1322, 1301, 1287, 1276, 1267, 1259, 1253, 1247, 1242, 1237}, // 10 temp delta
{ 1502, 1467, 1442, 1424, 1409, 1396, 1385, 1376, 1368, 1360}, // 15 temp delta
{ 1706, 1654, 1617, 1589, 1567, 1548, 1532, 1518, 1506, 1495}, // 20 temp delta
{ 1939, 1864, 1813, 1774, 1743, 1717, 1695, 1676, 1659, 1643}, // 25 temp delta
{ 2203, 2101, 2032, 1980, 1938, 1904, 1874, 1849, 1826, 1806} // 30 temp delta
};
// P9': The 2nd column (m values) are just initial values and will be updated based on
// full leakage @0.8V (a one time calculation). P9 will keep the same values.
int16_t G_wof_iddq_mult_table[WOF_IDDQ_MULT_TABLE_N][2] = {
{-70, 163},
{-65, 186},
{-60, 212},
{-55, 242},
{-50, 276},
{-45, 314},
{-40, 359},
{-35, 409},
{-30, 466},
{-25, 531},
{-20, 606},
{-15, 691},
{-10, 788},
{-5, 898},
{0, 1024},
{5, 1168},
{10, 1331},
{15, 1518},
{20, 1731},
{25, 1973},
{30, 2250}
};
//******************************************************************************
// Function Definitions
//******************************************************************************
/**
* call_wof_main
*
* Description: Performs the Initialization of the WOF infrastructure
* such that the WOF algorithm can run. This includes making
* sure the PGPE is ready to perform WOF calculations and enforcing
* when WOF should wait a tick to perform a calc or disable wof
* entirely. Called from amec_slave_smh.c::amec_slv_common_tasks_post.
* Param: None
*
* Return: None
*/
void call_wof_main( void )
{
// Timeout for VFRT to complete
static uint8_t L_vfrt_last_chance = MAX_VFRT_CHANCES_EVERY_TICK;
// Timeout for WOF Control to complete
static uint8_t L_wof_control_last_chance = MAX_WOF_CONTROL_CHANCES_EVERY_TICK;
// Variable to keep track of logging timeouts being ignored
// WOF runs every 500us all timeouts must be at least 1ms for PGPE
// to have time to set the bit to give ignore indication
static bool L_current_timeout_recorded = false;
// Variable to keep track of PState enablement to prevent setting/clearing
// wof_disabled bit every iteration.
static uint8_t L_pstate_protocol_off = 0;
// GpeRequest more than 1 extra time.
bool enable_success = false;
do
{
// If the init state says we just turned WOF on in pgpe, clear
// PGPE wof disabled bit
if(g_wof->wof_init_state == PGPE_WOF_ENABLED_NO_PREV_DATA)
{
set_clear_wof_disabled( CLEAR,
WOF_RC_PGPE_WOF_DISABLED,
ERC_WOF_PGPE_WOF_DISABLED );
}
// If error logged in callback, record now
if( g_wof->vfrt_callback_error )
{
INTR_TRAC_ERR("Got a bad RC in wof_vfrt_callback: 0x%x",
g_wof->wof_vfrt_req_rc);
set_clear_wof_disabled( SET,
WOF_RC_VFRT_REQ_FAILURE,
ERC_WOF_VFRT_REQ_FAILURE );
// After official error recorded, prevent this code
// from running from same setting of the var.
g_wof->vfrt_callback_error = 0;
}
// If the 405 turned WOF off on pgpe and it is the only bit set
// clear the bit so we can re-enable WOF
if( g_wof->pgpe_wof_off &&
(g_wof->wof_disabled == WOF_RC_PGPE_WOF_DISABLED) )
{
g_wof->pgpe_wof_off = 0;
set_clear_wof_disabled( CLEAR,
WOF_RC_PGPE_WOF_DISABLED,
ERC_WOF_PGPE_WOF_DISABLED );
}
// Make sure wof has not been disabled
if( g_wof->wof_disabled )
{
if( g_wof->pgpe_wof_disabled )
{
set_clear_wof_disabled( SET,
WOF_RC_PGPE_WOF_DISABLED,
ERC_WOF_PGPE_WOF_DISABLED );
g_wof->pgpe_wof_disabled = 0;
}
break;
}
// Make sure Pstate Protocol is on
if(G_proc_pstate_status != PSTATES_ENABLED)
{
if( L_pstate_protocol_off == 0 )
{
INTR_TRAC_ERR("WOF Disabled! Pstate Protocol off");
set_clear_wof_disabled( SET,
WOF_RC_PSTATE_PROTOCOL_OFF,
ERC_WOF_PSTATE_PROTOCOL_OFF );
L_pstate_protocol_off = 1;
}
// Since Pstates are off, break out
break;
}
else if(G_proc_pstate_status == PSTATES_ENABLED)
{
if( L_pstate_protocol_off == 1 )
{
INTR_TRAC_INFO("Pstate Protocol on! Clearing PSTATE_PROTOCOL_OFF");
set_clear_wof_disabled( CLEAR,
WOF_RC_PSTATE_PROTOCOL_OFF,
ERC_WOF_PSTATE_PROTOCOL_OFF );
L_pstate_protocol_off = 0;
}
}
// Ensure the OCC is active
if( IS_OCC_STATE_ACTIVE() )
{
// Make sure we are not disabled
if( !g_wof->wof_disabled &&
g_wof->wof_init_state < PGPE_WOF_ENABLED_NO_PREV_DATA )
{
switch( g_wof->wof_init_state )
{
// For each possible initialization state,
// do the appropriate action
case WOF_DISABLED:
// Reset timeouts for VFRT response and WOF control
L_vfrt_last_chance = MAX_VFRT_CHANCES;
L_wof_control_last_chance = MAX_WOF_CONTROL_CHANCES;
// reset OC ceff adder
g_wof->vdd_oc_ceff_add = 0;
sensor_update(AMECSENSOR_PTR(OCS_ADDR), (uint16_t)g_wof->vdd_oc_ceff_add);
// calculate initial vfrt, send gpeRequest
// Initial vfrt is the last vfrt in Main memory
send_initial_vfrt_to_pgpe();
break;
case INITIAL_VFRT_SENT_WAITING:
// Check if request is still processing.
// Init state updated in wof_vfrt_callback
if( (!async_request_is_idle(&G_wof_vfrt_req.request)) ||
(g_wof->vfrt_state != STANDBY) )
{
if( (L_vfrt_last_chance == 0) && (!ignore_pgpe_error()) )
{
INTR_TRAC_ERR("WOF Disabled!"
" Init VFRT request timeout");
set_clear_wof_disabled( SET,
WOF_RC_VFRT_REQ_TIMEOUT,
ERC_WOF_VFRT_REQ_TIMEOUT );
}
else if(L_vfrt_last_chance != 0)
{
if( L_vfrt_last_chance == 1 )
{
INTR_TRAC_INFO("initial VFRT NOT idle. Last chance out of %d chances",
MAX_VFRT_CHANCES);
}
L_vfrt_last_chance--;
}
else
{
// Wait forever for PGPE to respond
// Put a mark on the wall so we know we hit this state
if(!L_current_timeout_recorded)
{
INCREMENT_ERR_HISTORY(ERRH_VFRT_TIMEOUT_IGNORED);
L_current_timeout_recorded = TRUE;
}
}
}
break;
case INITIAL_VFRT_SUCCESS:
// We made it this far. Reset Last chance
L_vfrt_last_chance = MAX_VFRT_CHANCES;
// Send wof control on gpe request
// If enable_success returns true, init state was set
enable_success = enable_wof();
if( !enable_success )
{
// Treat as an error only if not currently ignoring PGPE failures
if( (L_wof_control_last_chance == 0) && (!ignore_pgpe_error()) )
{
INTR_TRAC_ERR("WOF Disabled! Control req timeout(1)");
set_clear_wof_disabled(SET,
WOF_RC_CONTROL_REQ_TIMEOUT,
ERC_WOF_CONTROL_REQ_TIMEOUT);
}
else if(L_wof_control_last_chance != 0)
{
if(L_wof_control_last_chance == 1 )
{
INTR_TRAC_ERR("Last chance for WOF control request(1) out of %d chances ",
MAX_WOF_CONTROL_CHANCES);
}
L_wof_control_last_chance--;
}
else
{
// Wait forever for PGPE to respond
// Put a mark on the wall so we know we hit this state
if(!L_current_timeout_recorded)
{
INCREMENT_ERR_HISTORY(ERRH_WOF_CONTROL_TIMEOUT_IGNORED);
L_current_timeout_recorded = TRUE;
}
}
}
else
{
// Reset the last chance variable
// Init state updated in enable_wof
L_wof_control_last_chance = MAX_WOF_CONTROL_CHANCES;
L_current_timeout_recorded = FALSE;
}
break;
case WOF_CONTROL_ON_SENT_WAITING:
// check if request is still processing.
if( !async_request_is_idle(&G_wof_control_req.request) )
{
// Treat as an error only if not currently ignoring PGPE failures
if( (L_wof_control_last_chance == 0) && (!ignore_pgpe_error()) )
{
INTR_TRAC_ERR("WOF Disabled! Control req timeout(2)");
set_clear_wof_disabled(SET,
WOF_RC_CONTROL_REQ_TIMEOUT,
ERC_WOF_CONTROL_REQ_TIMEOUT );
}
else if(L_wof_control_last_chance != 0)
{
if(L_wof_control_last_chance == 1 )
{
INTR_TRAC_ERR("Last chance for WOF control request(2) out of %d chances ",
MAX_WOF_CONTROL_CHANCES);
}
L_wof_control_last_chance--;
}
else
{
// Wait forever for PGPE to respond
// Put a mark on the wall so we know we hit this state
if(!L_current_timeout_recorded)
{
INCREMENT_ERR_HISTORY(ERRH_WOF_CONTROL_TIMEOUT_IGNORED);
L_current_timeout_recorded = TRUE;
}
}
}
else
{
L_current_timeout_recorded = FALSE;
}
// Init state updated in wof_control_callback
break;
default:
break;
} // Switch statement
}// initial state machine
// If we have made it to at least WOF enabled no previous data
// state run wof routine normally ensuring wof was not disabled
// in previous 5 states
if( (g_wof->wof_init_state >= PGPE_WOF_ENABLED_NO_PREV_DATA) &&
!g_wof->wof_disabled )
{
// Normal execution of wof algorithm
if( (!async_request_is_idle(&G_wof_vfrt_req.request)) ||
(g_wof->vfrt_state != STANDBY) )
{
if( L_vfrt_last_chance == 0 )
{
// Treat as an error only if not currently ignoring PGPE failures
if(!ignore_pgpe_error())
{
INTR_TRAC_ERR("WOF Disabled! VFRT req timeout");
set_clear_wof_disabled(SET,
WOF_RC_VFRT_REQ_TIMEOUT,
ERC_WOF_VFRT_REQ_TIMEOUT);
}
else
{
// Wait forever for PGPE to respond
// Put a mark on the wall so we know we hit this state
if(!L_current_timeout_recorded)
{
INCREMENT_ERR_HISTORY(ERRH_VFRT_TIMEOUT_IGNORED);
L_current_timeout_recorded = TRUE;
}
}
}
else
{
if( L_vfrt_last_chance == 1 )
{
INTR_TRAC_INFO("VFRT NOT idle. Last chance out of %d chances",
MAX_VFRT_CHANCES);
}
L_vfrt_last_chance--;
}
}
else
{
L_current_timeout_recorded = FALSE;
// Request is idle. Run wof algorithm
wof_main();
L_vfrt_last_chance = MAX_VFRT_CHANCES;
// Finally make sure we are in the fully enabled state
if( g_wof->wof_init_state == PGPE_WOF_ENABLED_NO_PREV_DATA )
{
g_wof->wof_init_state = WOF_ENABLED;
// Set the the frequency ranges
errlHndl_t l_errl = amec_set_freq_range(CURRENT_MODE());
if(l_errl)
{
INTR_TRAC_ERR("call_wof_main: amec_set_freq_range reported an error");
commitErrl( &l_errl);
}
}
}
} // >= PGPE_WOF_ENABLED_NO_PREV_DATA
} // IS_OCC_STATE_ACTIVE
} while( 0 );
}
/**
* wof_main
*
* Description: Main Wof algorithm
*
* Param: None
*
* Return: None
*/
void wof_main( void )
{
// Some sensors may be updated from PGPE data so we must read PGPE data before reading sensors
// Read out PGPE data from shared SRAM
read_shared_sram();
// Read out the sensor data needed for calculations
read_sensor_data();
// Calculate the core voltage per quad
calculate_core_voltage();
// Calculate the core leakage across the entire Proc
calculate_core_leakage();
// Calculate the nest leakage for the entire system
calculate_nest_leakage();
// Calculate the AC currents
calculate_AC_currents();
// Calculate ceff_ratio_vdd and ceff_ratio_vdn
calculate_ceff_ratio_vdd();
calculate_ceff_ratio_vdn();
// Calculate how many steps from the beginning for VDD, VDN, and active quads
g_wof->vdn_step_from_start =
calculate_step_from_start( g_wof->ceff_ratio_vdn,
g_wof->vdn_step,
g_wof->vdn_start,
g_wof->vdn_size );
g_wof->vdd_step_from_start =
calculate_step_from_start( g_wof->ceff_ratio_vdd,
g_wof->vdd_step,
g_wof->vdd_start,
g_wof->vdd_size );
g_wof->quad_step_from_start = calc_quad_step_from_start();
// Compute the Main Memory address of the desired VFRT table given
// the calculated VDN, VDD, and Quad steps
g_wof->next_vfrt_main_mem_addr = calc_vfrt_mainstore_addr();
// Send the new vfrt to the PGPE
send_vfrt_to_pgpe( g_wof->next_vfrt_main_mem_addr );
}
/**
* calculate_step_from_start
*
* Description: Calculates the step number for the current VDN/VDD
*
* Param[in]: i_ceff_vdx_ratio - The current Ceff_vdd or Ceff_vdn_ratio
* to calculate the step for.
* Param[in]: i_step_size - The size of each step.
* Param[in]: i_min_ceff - The minimum step number for this VDN/VDD
* Param[in]: i_max_step - The maximum step number for this VDN/VDD
*
* Return: The calculated step for current Ceff_vdd/Ceff_vdn
*/
uint16_t calculate_step_from_start(uint16_t i_ceff_vdx_ratio,
uint16_t i_step_size,
uint16_t i_min_ceff,
uint16_t i_max_step )
{
uint16_t l_current_step;
// Ensure ceff is at least the min step
if( (i_ceff_vdx_ratio <= i_min_ceff) || (i_step_size == 0) )
{
l_current_step = 0;
}
else
{
// Add step size to current vdd/vdn to round up.
// -1 to prevent overshoot when i_ceff_vdx_ratio is equal to Ceff table value
l_current_step = i_ceff_vdx_ratio + i_step_size - 1;
// Subtract the starting ceff to skip the 0 table entry
l_current_step -= i_min_ceff;
// Divide by step size to determine how many from the 0 entry ceff is
l_current_step /= i_step_size;
// If the calculated step is greater than the max step, use max step
if( l_current_step >= i_max_step )
{
// Since function returns number of steps from start
// (first entry is 0 from start) subtract 1.
l_current_step = i_max_step-1;
}
}
return l_current_step;
}
/**
* calc_quad_step_from_start
*
* Description: Calculates the step number for the current number
* of active quads
*
* Return: The calculated step for current active quads
*/
uint8_t calc_quad_step_from_start( void )
{
return (G_wof_header.active_quads_size == ACTIVE_QUAD_SZ_MIN) ? 0 :
(g_wof->num_active_quads - 1);
}
/**
* calc_vfrt_mainstore_address
*
* Description: Calculates the VFRT address based on the Ceff vdd/vdn and quad
* steps.
*
* Return: The desired VFRT main memory address
*/
uint32_t calc_vfrt_mainstore_addr( void )
{
static bool L_trace_char_test = true;
// skip calculation and return first table if WOF Char testing is enabled
if(G_internal_flags & INT_FLAG_ENABLE_WOF_CHAR_TEST)
{
if(L_trace_char_test)
{
INTR_TRAC_IMP("Entered WOF char testing using first VRT!");
L_trace_char_test = false;
}
g_wof->vfrt_mm_offset = 0;
}
else
{
if(!L_trace_char_test)
{
INTR_TRAC_IMP("Exited WOF char testing calculating VRT!");
L_trace_char_test = true;
}
// Wof tables address calculation
// (Base_addr +
// (sizeof VFRT * (total active quads * ( (g_wof->vdn_step_from_start * vdd_size) + (g_wof->vdd_step_from_start) ) + (g_wof->quad_step_from_start))))
g_wof->vfrt_mm_offset = g_wof->vfrt_block_size *
(( g_wof->active_quads_size *
((g_wof->vdn_step_from_start * g_wof->vdd_size) +
g_wof->vdd_step_from_start) ) + g_wof->quad_step_from_start);
}
// Skip the wof header at the beginning of wof tables
uint32_t wof_tables_base = g_wof->vfrt_tbls_main_mem_addr + WOF_HEADER_SIZE;
return wof_tables_base + g_wof->vfrt_mm_offset;
}
/**
* copy_vfrt_to_sram_callback
*
* Description: Call back function to BCE request to copy VFRT into SRAM
* ping/pong buffer. This call will also tell the PGPE
* that a new VFRT is available
*
* Param[in]: i_parms - pointer to a struct that will hold data necessary to
* the calculation.
* -Pointer to vfrt table temp buffer
*/
void copy_vfrt_to_sram_callback( void )
{
/*
*
* find out which ping pong buffer to use
* copy the vfrt to said ping pong buffer
* save current vfrt address to global
* send IPC command to pgpe to notify of new ping/pong vfrt address
*/
// Static variable to trac which buffer is open for use
// 0 = PING; 1 = PONG;
uint8_t * l_buffer_address = G_sram_vfrt_ping_buffer;
if(g_wof->curr_ping_pong_buf == (uint32_t)G_sram_vfrt_ping_buffer)
{
// Switch to pong buffer
l_buffer_address = G_sram_vfrt_pong_buffer;
}
else
{
// Switch to ping buffer
l_buffer_address = G_sram_vfrt_ping_buffer;
}
// Update global "next" ping pong buffer for callback function
g_wof->next_ping_pong_buf = (uint32_t)l_buffer_address;
// Copy the vfrt data into the buffer
memcpy( l_buffer_address,
&G_vfrt_temp_buff,
g_wof->vfrt_block_size );
// Set the parameters for the GpeRequest
G_wof_vfrt_parms.homer_vfrt_ptr = (HomerVFRTLayout_t*)l_buffer_address;
G_wof_vfrt_parms.active_quads = g_wof->req_active_quad_update;
if( g_wof->vfrt_state != STANDBY )
{
// Set vfrt state to let OCC know it needs to schedule the IPC command
g_wof->vfrt_state = NEED_TO_SCHEDULE;
}
}
/**
* wof_vfrt_callback
*
* Description: Callback function for G_wof_vfrt_req GPE request to
* confirm the new VFRT is being used by the PGPE and
* record the switch on the 405. Also updates the
* initialization
*/
void wof_vfrt_callback( void )
{
// Update the VFRT state to indicate a new IPC message can be
// scheduled regardless of the RC of the previous one.
g_wof->vfrt_state = STANDBY;
// Confirm the WOF VFRT PGPE request has completed with no errors
if( G_wof_vfrt_parms.msg_cb.rc == PGPE_WOF_RC_VFRT_QUAD_MISMATCH )
{
// Rereading OCC-SRAM to update requested active quads
read_req_active_quads();
}
else if( G_wof_vfrt_parms.msg_cb.rc == PGPE_RC_SUCCESS )
{
// GpeRequest went through successfully. update global ping pong buffer
g_wof->curr_ping_pong_buf = g_wof->next_ping_pong_buf;
// Update previous active quads
g_wof->prev_req_active_quads = g_wof->req_active_quad_update;
// Update current vfrt_main_mem_address
g_wof->curr_vfrt_main_mem_addr = g_wof->next_vfrt_main_mem_addr;
// Update the wof_init_state based off the current state
if( g_wof->wof_init_state == INITIAL_VFRT_SENT_WAITING )
{
g_wof->wof_init_state = INITIAL_VFRT_SUCCESS;
}
}
else
{
// Disable WOF
g_wof->vfrt_callback_error = 1;
g_wof->wof_vfrt_req_rc = G_wof_vfrt_parms.msg_cb.rc;
}
}
/**
* send_vfrt_to_pgpe
*
* Description: Function to copy new VFRT from Mainstore to local SRAM buffer
* and calls copy_vfrt_to_sram_callback function to send new VFRT
* to the PGPE
* Note: If desired VFRT is the same as previous, skip.
*
* Param[in]: i_vfrt_main_mem_addr - Address of the desired vfrt table.
*/
void send_vfrt_to_pgpe( uint32_t i_vfrt_main_mem_addr )
{
int l_ssxrc = SSX_OK;
do
{
// First check if the address is 128-byte aligned. error if not.
if( i_vfrt_main_mem_addr % 128 )
{
INTR_TRAC_ERR("VFRT Main Memory address NOT 128-byte aligned:"
" 0x%08x", i_vfrt_main_mem_addr);
set_clear_wof_disabled(SET,
WOF_RC_VFRT_ALIGNMENT_ERROR,
ERC_WOF_VFRT_ALIGNMENT_ERROR);
break;
}
// Check if PGPE explicitely requested a new vfrt
ocb_occflg_t occ_flags = {0};
occ_flags.value = in32(OCB_OCCFLG);
if( ((i_vfrt_main_mem_addr == g_wof->curr_vfrt_main_mem_addr ) &&
(g_wof->req_active_quad_update ==
g_wof->prev_req_active_quads)) &&
(!occ_flags.fields.active_quad_update) )
{
// VFRT and requested active quads are unchanged.
break;
}
// Either the Main memory address changed or req active quads changed
// get VFRT based on new values
else
{
// Create request
l_ssxrc = bce_request_create(
&G_vfrt_req, // block copy object
&G_pba_bcde_queue, // main to sram copy engine
i_vfrt_main_mem_addr, //mainstore address
(uint32_t) &G_vfrt_temp_buff, // SRAM start address
MIN_BCE_REQ_SIZE, // size of copy
SSX_WAIT_FOREVER, // no timeout
(AsyncRequestCallback)copy_vfrt_to_sram_callback,
NULL,
ASYNC_CALLBACK_IMMEDIATE );
if(l_ssxrc != SSX_OK)
{
INTR_TRAC_ERR("send_vfrt_to_pgpe: BCDE request create failure rc=[%08X]", -l_ssxrc);
break;
}
// Make sure we are in correct vfrt state
if( g_wof->vfrt_state == STANDBY )
{
// Set the VFRT state to ensure asynchronous order of operations
g_wof->vfrt_state = SEND_INIT;
// Do the actual copy
l_ssxrc = bce_request_schedule( &G_vfrt_req );
if(l_ssxrc != SSX_OK)
{
INTR_TRAC_ERR("send_vfrt_to_pgpe: BCE request schedule failure rc=[%08X]", -l_ssxrc);
break;
}
}
}
}while( 0 );
// Check for errors and log, if any
if( l_ssxrc != SSX_OK )
{
// Formally disable WOF
set_clear_wof_disabled( SET,
WOF_RC_IPC_FAILURE,
ERC_WOF_IPC_FAILURE );
return;
}
}
/**
* read_shared_sram
*
* Description: Read out data from OCC-PGPE shared SRAM and saves the
* data for the current iteration of the WOF algorithm
*/
void read_shared_sram( void )
{
// Get the actual quad states
G_quad_state_0.value = in64(g_wof->quad_state_0_addr);
G_quad_state_1.value = in64(g_wof->quad_state_1_addr);
// Read f_clip, v_clip, f_ratio, and v_ratio
pgpe_wof_state_t l_wofstate;
l_wofstate.value = in64(g_wof->pgpe_wof_state_addr);
g_wof->f_clip_ps = l_wofstate.fields.fclip_ps;
g_wof->v_clip = l_wofstate.fields.vclip_mv;
// Update Fclip Freq and Vratio for P9 only. P9 prime uses values updated in read_pgpe_produced_wof_values()
if( (!G_pgpe_shared_sram_V_I_readings) ||
(G_internal_flags & INT_FLAG_DISABLE_CEFF_TRACKING) )
{
g_wof->v_ratio = l_wofstate.fields.vratio;
sensor_update(AMECSENSOR_PTR(VRATIO), (uint16_t)l_wofstate.fields.vratio);
// convert f_clip_ps from Pstate to frequency(mHz)
g_wof->f_clip_freq = (proc_pstate2freq(g_wof->f_clip_ps))/1000;
}
g_wof->f_ratio = 1;
// the PGPE produced WOF values were already read in this tick from amec_update_avsbus_sensors()
// required to read them in every tick regardless of WOF running so voltage and current sensors
// are updated even when WOF isn't running
// Get the requested active quad update
read_req_active_quads();
// merge the 16-bit active_cores field from quad state 0 and the 16-bit
// active_cores field from quad state 1 and save it to amec.
g_wof->core_pwr_on =
(((uint32_t)G_quad_state_0.fields.active_cores) << 16)
| ((uint32_t)G_quad_state_1.fields.active_cores);
// Clear out current quad pstates
memset(g_wof->quad_x_pstates, 0 , MAXIMUM_QUADS);
// Add the quad states to the global quad state array for easy looping.
g_wof->quad_x_pstates[0] = (uint8_t)G_quad_state_0.fields.quad0_pstate;
g_wof->quad_x_pstates[1] = (uint8_t)G_quad_state_0.fields.quad1_pstate;
g_wof->quad_x_pstates[2] = (uint8_t)G_quad_state_0.fields.quad2_pstate;
g_wof->quad_x_pstates[3] = (uint8_t)G_quad_state_0.fields.quad3_pstate;
g_wof->quad_x_pstates[4] = (uint8_t)G_quad_state_1.fields.quad4_pstate;
g_wof->quad_x_pstates[5] = (uint8_t)G_quad_state_1.fields.quad5_pstate;
// Save IVRM bit vector states to amec
// NOTE: the ivrm_state field in both quad state 0 and quad state 1
// double words should contain the same data.
g_wof->quad_ivrm_states =
(((uint8_t)G_quad_state_0.fields.ivrm_state) << 4)
| ((uint8_t)G_quad_state_1.fields.ivrm_state);
}
/**
* read_pgpe_produced_wof_values
*
* Description: Read the PGPE Produced WOF values from OCC-PGPE shared SRAM and
* update sensors
*/
void read_pgpe_produced_wof_values( void )
{
// Read in OCS bits from OCC Flag 0 register
uint32_t occ_flags0 = 0;
occ_flags0 = in32(OCB_OCCFLG);
g_wof->ocs_dirty = (uint8_t)(occ_flags0 & (OCS_PGPE_DIRTY_MASK | OCS_PGPE_DIRTY_TYPE_MASK));
// INC counter for value of ocs_dirty
if(g_wof->ocs_dirty == 0) // not dirty
g_wof->ocs_not_dirty_count++;
else if(g_wof->ocs_dirty == OCS_PGPE_DIRTY_TYPE_MASK) // not dirty, type 1. PGPE shouldn't be setting this
g_wof->ocs_not_dirty_type1_count++;
else if(g_wof->ocs_dirty == OCS_PGPE_DIRTY_MASK) // dirty type 0 (hold)
g_wof->ocs_dirty_type0_count++;
else if(g_wof->ocs_dirty == (OCS_PGPE_DIRTY_MASK | OCS_PGPE_DIRTY_TYPE_MASK)) // dirty type 1 (act)
g_wof->ocs_dirty_type1_count++;
else
INTR_TRAC_ERR("???????? Invalid ocs_dirty[%d]", g_wof->ocs_dirty);
// Update V/I from PGPE
uint16_t l_voltage = 0;
uint16_t l_current = 0;
uint32_t l_freq = 0;
pgpe_wof_values_t l_PgpeWofValues;
l_PgpeWofValues.dw0.value = in64(G_pgpe_header.pgpe_produced_wof_values_addr);
l_PgpeWofValues.dw1.value = in64(G_pgpe_header.pgpe_produced_wof_values_addr + 0x08);
l_PgpeWofValues.dw2.value = in64(G_pgpe_header.pgpe_produced_wof_values_addr + 0x10);
l_PgpeWofValues.dw3.value = in64(G_pgpe_header.pgpe_produced_wof_values_addr + 0x18);
// save Vdd voltage to sensor
l_voltage = (uint16_t)l_PgpeWofValues.dw2.fields.vdd_avg_mv;
if (l_voltage != 0)
{
// Voltage value stored in the sensor should be in 100uV (mV scale -1)
l_voltage *= 10;
sensor_update(AMECSENSOR_PTR(VOLTVDD), l_voltage);
}
// save Vdn voltage to sensor
l_voltage = (uint16_t)l_PgpeWofValues.dw2.fields.vdn_avg_mv;
if (l_voltage != 0)
{
// Voltage value stored in the sensor should be in 100uV (mV scale -1)
l_voltage *= 10;
sensor_update(AMECSENSOR_PTR(VOLTVDN), l_voltage);
}
// don't use Vdd current from PGPE if it was enabled for OCC to read from AVSbus
if(!(G_internal_flags & INT_FLAG_ENABLE_VDD_CURRENT_READ))
{
// Save Vdd current to sensor
l_current = (uint16_t)l_PgpeWofValues.dw1.fields.idd_avg_ma;
if (l_current != 0)
{
// Current value stored in the sensor should be in 10mA (A scale -2)
// Reading from SRAM is already in 10mA
sensor_update(AMECSENSOR_PTR(CURVDD), l_current);
}
}
// Save Vdn current to sensor
l_current = (uint16_t)l_PgpeWofValues.dw1.fields.idn_avg_ma;
if (l_current != 0)
{
// Current value stored in the sensor should be in 10mA (A scale -2)
// Reading from SRAM is already in 10mA
sensor_update(AMECSENSOR_PTR(CURVDN), l_current);
}
// Update the chip voltage and power sensors
update_avsbus_power_sensors(AVSBUS_VDD);
update_avsbus_power_sensors(AVSBUS_VDN);
// populate values used by WOF alg
// these are only used for Ceff frequency tracking
if(!(G_internal_flags & INT_FLAG_DISABLE_CEFF_TRACKING))
{
// Average Frequency
l_freq = proc_pstate2freq((Pstate)l_PgpeWofValues.dw0.fields.average_frequency_pstate);
// value returned in kHz, save in MHz
g_wof->c_ratio_vdd_freq = (l_freq / 1000);
g_wof->f_clip_freq = g_wof->c_ratio_vdd_freq;
g_wof->v_ratio = l_PgpeWofValues.dw0.fields.vratio_avg;