405 Side GPU Core Temp Collection

Change-Id: Ia1b10f5208c49ba168dcf338f0cbeb2c4ab46971 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44982 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
open-power · Aug 25, 2017 · 3f57751 · 3f57751
1 parent 8e2f38a
commit 3f57751
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Showing 9 changed files with 379 additions and 365 deletions.
diff --git a/src/common/gpu_structs.h b/src/common/gpu_structs.h
@@ -57,18 +57,19 @@ typedef enum
 typedef enum
 {
     GPU_REQ_INIT                        = 0x01, // Init interrupt registers
-    GPU_REQ_READ_CAPS_START             = 0x02, // Start reading capabilities
-    GPU_REQ_READ_CAPS_STOP              = 0x03,
-    GPU_REQ_READ_CAPS                   = 0x04,
-    GPU_REQ_READ_TEMP_SIMPLE_START      = 0x05, // Start reading GPU information
-    GPU_REQ_READ_TEMP_SIMPLE_STOP       = 0x06, // Read GPU temp register
-    GPU_REQ_READ_TEMP_SIMPLE            = 0x07, // Start reading GPU temperature
-    GPU_REQ_READ_TEMP_START             = 0x08, // Start reading GPU information
-    GPU_REQ_READ_TEMP_STOP              = 0x09, // Read GPU temp register
-    GPU_REQ_READ_TEMP                   = 0x0A, // Start reading GPU temperature
-    GPU_REQ_READ_PWR_LIMIT_START        = 0x0B, // Start reading GPU information
-    GPU_REQ_READ_PWR_LIMIT_STOP         = 0x0C, // Read GPU temp register
-    GPU_REQ_READ_PWR_LIMIT              = 0x0D, // Start reading pwr limit
+    GPU_REQ_READ_TEMP_START             = 0x02, // Start reading GPU information
+    GPU_REQ_READ_TEMP_FINISH            = 0x03, // Read GPU temp register
+    GPU_REQ_READ_MEM_TEMP_START         = 0x04, // Initiate memory temp reading
+    GPU_REQ_READ_MEM_TEMP_2             = 0x05, // mem temp step 2
+    GPU_REQ_READ_MEM_TEMP_3             = 0x06, // mem temp step 3
+    GPU_REQ_READ_MEM_TEMP_FINISH        = 0x07, // Get memory temp reading
+    GPU_REQ_READ_CAPS_START             = 0x08, // Start reading capabilities
+    GPU_REQ_READ_CAPS_2                 = 0x09, // Start reading capabilities
+    GPU_REQ_READ_CAPS_3                 = 0x0A, // Start reading capabilities
+    GPU_REQ_READ_CAPS_FINISH            = 0x0B,
+    GPU_REQ_READ_PWR_LIMIT_START        = 0x0C, // Start reading GPU information
+    GPU_REQ_READ_PWR_LIMIT_STOP         = 0x0D, // Read GPU temp register
+    GPU_REQ_READ_PWR_LIMIT              = 0x0E, // Start reading pwr limit
     GPU_REQ_RESET                       = 0x60, // Reset
 } gpu_op_req_e;
 
@@ -78,7 +79,7 @@ typedef struct
   GpeErrorStruct error;
   uint8_t gpu_id;
   uint8_t operation;
-  uint32_t data[MAX_GPUS];
+  uint64_t data;
 } gpu_sm_args_t;
 
 

diff --git a/src/occ_405/amec/amec_sensors_power.c b/src/occ_405/amec/amec_sensors_power.c
@@ -75,6 +75,7 @@ extern bool    G_vrm_thermal_monitoring;
 extern PWR_READING_TYPE  G_pwr_reading_type;
 extern bool    G_apss_present;
 extern OCCPstateParmBlock G_oppb;
+extern task_t G_task_table[TASK_END];
 
 //*************************************************************************/
 // Code
@@ -826,6 +827,7 @@ void amec_update_gpu_configuration(void)
             {
                // GPUs are present enable monitoring
                G_gpu_monitoring_allowed = TRUE;
+               G_task_table[TASK_ID_GPU_SM].flags = GPU_RTL_FLAGS;
             }
             G_first_sys_gpu_config = l_valid_bitmask_sys;
             G_first_num_gpus_sys = l_num_gpus_sys;