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p9_sbe_chiplet_reset.C
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p9_sbe_chiplet_reset.C
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C $ */
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
//------------------------------------------------------------------------------
/// @file p9_sbe_chiplet_reset.C
///
/// @brief Steps:-
/// 1) Identify Partical good chiplet and configure Multicasting register
/// 2) Similar way, Configure hang pulse counter for Nest/MC/OBus/XBus/PCIe
/// 3) Similar way, set fence for Nest and MC chiplet
/// 4) Similar way, Reset sys.config and OPCG setting for Nest and MC chiplet in sync mode
///
/// Done
//------------------------------------------------------------------------------
// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com>
// *HWP HW Backup Owner : Srinivas V. Naga <srinivan@in.ibm.com>
// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com>
// *HWP Team : Perv
// *HWP Level : 2
// *HWP Consumed by : SBE
//------------------------------------------------------------------------------
//## auto_generated
#include "p9_sbe_chiplet_reset.H"
//## auto_generated
#include "p9_const_common.H"
#include <p9_perv_scom_addresses.H>
#include <p9_perv_scom_addresses_fld.H>
#include <p9_perv_sbe_cmn.H>
static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt);
static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_net_cntl_setup(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt);
static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_MC_XBUS(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
const fapi2::buffer<uint32_t> i_clk_mux_value);
static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_obus(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
const fapi2::buffer<uint32_t> i_clk_mux_value);
static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
const fapi2::buffer<uint32_t> i_clk_mux_value);
static fapi2::ReturnCode p9_sbe_chiplet_reset_div_clk_bypass(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
static fapi2::ReturnCode p9_sbe_chiplet_reset_enable_listen_to_sync(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
const bool i_enable);
static fapi2::ReturnCode p9_sbe_chiplet_reset_hsspowergate(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_async_reset_setup(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
const bool i_drop);
static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_ob_async_reset(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
static fapi2::ReturnCode
p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt);
static fapi2::ReturnCode p9_sbe_chiplet_reset_pll_setup(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
const bool i_enable);
static fapi2::ReturnCode p9_sbe_chiplet_reset_scan0_call(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
static fapi2::ReturnCode p9_sbe_chiplet_reset_setup(const
fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
static fapi2::ReturnCode p9_sbe_chiplet_reset_setup_iop_logic(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
static fapi2::ReturnCode p9_sbe_chiplet_reset_all_obus_scan0(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
static fapi2::ReturnCode p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
static fapi2::ReturnCode p9_sbe_chiplet_reset_assert_scan_clk(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
fapi2::ReturnCode p9_sbe_chiplet_reset(const
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
// Local variable
uint8_t l_mc_sync_mode = 0;
uint8_t l_pll_bypass = 0;
fapi2::buffer<uint8_t> l_read_attr;
#ifndef __PPE__
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
uint8_t l_attr_system_ipl_phase;
#endif
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
uint8_t attr_force_all = 0;
uint8_t l_use_dmi_buckets = 0;
// Created Vectors before hand instead of calling getChildren for each usage
auto l_perv_func_WO_Core_Cache = i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(
static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
fapi2::TARGET_STATE_FUNCTIONAL);
auto l_perv_func = i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(
static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES |
fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC |
fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
fapi2::TARGET_STATE_FUNCTIONAL);
auto l_perv_pres = i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(
static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES |
fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC |
fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
fapi2::TARGET_STATE_PRESENT);
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode),
"Error from FAPI_ATTR_GET (ATTR_MC_SYNC_MODE)");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_pll_bypass),
"Error from FAPI_ATTR_GET (ATTR_NEST_MEM_X_O_PCI_BYPASS)");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS, i_target_chip, l_use_dmi_buckets),
"Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS)");
FAPI_INF("p9_sbe_chiplet_reset: Entering ...");
FAPI_DBG("Do a scan0 to all obus chiplets independent of PG information");
for (auto& obus : l_perv_pres)
{
uint32_t l_chipletID = obus.getChipletNumber();
if(l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID)
{
FAPI_TRY(p9_sbe_chiplet_reset_all_obus_scan0(obus));
}
}
// Setup Perv into MCG0
FAPI_DBG("Adding PERV to Multicast group 0");
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_MULTICAST_GROUP_1,
p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0));
// Setup cache/cores multicast groups only in FORCE_ALL_CORE mode.
// If not in FORCE_ALL_CORE mode, cache/core multicast groups will be setup
// in preparation of p9_sbe_select_ex in preparation of istep 4.
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES,
FAPI_SYSTEM,
attr_force_all));
if (attr_force_all)
{
for (auto& targ : l_perv_func)
{
// Cache & Core - Functional
uint32_t l_chipletID = targ.getChipletNumber();
if((l_chipletID >= EQ0_CHIPLET_ID && l_chipletID <= EQ5_CHIPLET_ID) ||
(l_chipletID >= EC0_CHIPLET_ID && l_chipletID <= EC23_CHIPLET_ID))
{
// Configuring chiplet multicasting registers..
FAPI_DBG("Configuring cache/core chiplet multicasting registers");
FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(targ));
}
}
}
// do not do other setup if not PPE and cache_contained mode.
#ifndef __PPE__
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys,
l_attr_system_ipl_phase));
if (l_attr_system_ipl_phase !=
fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) //Skip for cache contained.
{
#endif
uint8_t l_is_p9c;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9C_LOGIC_ONLY,
i_target_chip,
l_is_p9c));
// NEST OBUS XBUS PCI MC - Functional
for (auto& targ : l_perv_func_WO_Core_Cache)
{
FAPI_DBG("Configuring multicasting registers for Mc,Nest,Xb,Obus,pcie chiplets");
// if in ASYNC mode DO NOT add to multicast groups because the chiplet is non
// responsive. Wait until clocks are started up in hostboot
uint32_t l_chipletID = targ.getChipletNumber();
if((l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) &&
(!l_mc_sync_mode && !l_use_dmi_buckets))
{
continue;
}
FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(targ));
}
// NEST OBUS XBUS PCI MC CACHE CORE - Functional
for (auto& targ : l_perv_func)
{
// Configuring NET control registers into Default required value
FAPI_DBG("Restore NET_CTRL0&1 init value - for all chiplets except TP");
FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_net_cntl_setup(targ));
FAPI_DBG("Setup hang pulse counter for all perv chiplet except TP");
FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(targ));
}
FAPI_DBG("Clock mux settings");
for (auto& targ : l_perv_pres)
{
fapi2::buffer<uint32_t> l_read_attr;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_read_attr));
uint32_t l_chipletID = targ.getChipletNumber();
// MC & XBUS
if((l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) || (l_chipletID == XB_CHIPLET_ID ))
{
FAPI_DBG("Mux settings for Mc/Xbus chiplet");
FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_MC_XBUS(targ, l_read_attr));
}
// OBUS
else if(l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID)
{
FAPI_DBG("Mux settings for OB chiplet");
FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_obus(targ, l_read_attr));
}
// PCI
else if(l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID)
{
FAPI_DBG("Mux settings for Pcie chiplet");
FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_pcie(targ, l_read_attr));
}
}
FAPI_DBG("Sector buffer strength and pulse mode setup");
// MC XBUS OBUS PCI
for (auto& targ : l_perv_func_WO_Core_Cache)
{
uint32_t l_chipletID = targ.getChipletNumber();
if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID)
{
continue;
}
FAPI_TRY(p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup(targ));
}
//Perv
for (auto& targ : l_perv_pres)
{
uint32_t l_chipletID = targ.getChipletNumber();
// Setting up partial good fence drop and resetting chiplet.
FAPI_DBG("PLL Setup : Enable pll");
FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(targ, true));
if(l_chipletID == N3_CHIPLET_ID)
{
FAPI_DBG("Drop clk async reset for N3 chiplet");
FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(targ));
}
if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID)
{
FAPI_DBG("Drop clk async reset for Mc chiplet");
FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(targ, true));
}
}
fapi2::delay(10000, (40 * 400));
// Perv
for (auto& targ : l_perv_pres)
{
// Setting up partial good fence drop and resetting chiplet.
FAPI_DBG("PLL setup : Disable pll");
FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(targ, false));
}
for (auto& targ : l_perv_pres)
{
// MC
uint32_t l_chipletID = targ.getChipletNumber();
if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID)
{
FAPI_DBG("Raise clk async reset for Mc chiplet");
FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(targ, false));
}
}
for (auto& targ : l_perv_func)
{
// OBUS
uint32_t l_chipletID = targ.getChipletNumber();
if(l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID)
{
FAPI_DBG("Drop clk async reset for N3, Mc and Obus chiplets");
FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(targ));
}
}
for (auto& targ : l_perv_func)
{
//MC
uint32_t l_chipletID = targ.getChipletNumber();
if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID)
{
FAPI_DBG("Drop clk_div_bypass for Mc chiplet");
FAPI_TRY(p9_sbe_chiplet_reset_div_clk_bypass(targ));
}
}
// Perv
for (auto& targ : l_perv_func)
{
FAPI_DBG("Enable chiplet and reset error register");
FAPI_TRY(p9_sbe_chiplet_reset_setup(targ));
}
// Perv without Core/Cache
for (auto& targ : l_perv_func_WO_Core_Cache)
{
FAPI_DBG("Drop lvltrans fence and endpoint reset");
FAPI_TRY(p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset(
targ));
}
// Perv without Core/Cache
for (auto& targ : l_perv_func_WO_Core_Cache)
{
FAPI_DBG("Initialize OPCG registers for Nest,MC,XB,OB,PCIe");
FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg(targ));
}
// NEST OBUS PCI XBUS
for (auto& targ : l_perv_func_WO_Core_Cache)
{
uint32_t l_chipletID = targ.getChipletNumber();
if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID)
{
continue;
}
FAPI_DBG("Enable listen to sync for NEST,OB,XB,PCIe");
FAPI_TRY(p9_sbe_chiplet_reset_enable_listen_to_sync(targ, true));
}
// MC OBUS PCI XBUS
for (auto& targ : l_perv_func_WO_Core_Cache)
{
uint32_t l_chipletID = targ.getChipletNumber();
if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID)
{
continue;
}
FAPI_DBG("Disable listen_to_sync for MC,XB,OB,PCIe");
FAPI_TRY(p9_sbe_chiplet_reset_enable_listen_to_sync(targ, false));
}
FAPI_DBG("Set Chip-wide HSSPORWREN gate");
FAPI_TRY(p9_sbe_chiplet_reset_hsspowergate(i_target_chip));
// PCI
for (auto& targ : l_perv_func)
{
//PCI
uint32_t l_chipletID = targ.getChipletNumber();
if(l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID)
{
FAPI_DBG("Setup IOP Logic for PCIe");
FAPI_TRY(p9_sbe_chiplet_reset_setup_iop_logic(targ));
}
}
// lower scan ratio for chiplets operating at PLL speed
// Nest: on pll, if not in bypass
// MC: on pll, if not in bypsas, and if in sync mode
if (!l_pll_bypass)
{
if (l_mc_sync_mode || l_use_dmi_buckets)
{
for (auto& targ : l_perv_func)
{
// NEST MC
uint32_t l_chipletID = targ.getChipletNumber();
if((l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID) ||
(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID))
{
FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(targ));
}
}
}
else
{
for (auto& targ : l_perv_func)
{
// NEST
uint32_t l_chipletID = targ.getChipletNumber();
if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID)
{
FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(targ));
}
}
}
}
FAPI_DBG("reading ec_level attr HW404176_ASSERT_SCAN_CLK");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK,
i_target_chip, l_read_attr));
// Perv without Core/Cache
for (auto& targ : l_perv_func_WO_Core_Cache)
{
FAPI_TRY(p9_sbe_chiplet_reset_scan0_call(targ));
uint32_t l_chipletID = targ.getChipletNumber();
if((l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) // cumulus chip & MC chiplet
{
FAPI_DBG("assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1 for cumulus chip Mc chiplet");
FAPI_TRY(p9_sbe_chiplet_reset_assert_scan_clk(targ));
}
}
for (auto& targ : l_perv_func)
{
//MC
uint32_t l_chipletID = targ.getChipletNumber();
if (l_is_p9c && (l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID))
{
FAPI_DBG("Set TC_IOM_FASTX2_RATIO_DC");
FAPI_TRY(fapi2::putScom(targ,
PERV_CPLT_CONF1_OR,
p9SbeChipletReset::MC_CPLT_CONF1_FASTX2_RATIO_MASK));
}
}
#ifndef __PPE__
}
#endif
FAPI_INF("p9_sbe_chiplet_reset: Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1 for cumulus chip Mc chiplet
///
/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target
/// @return FAPI2_RC_SUCCESS if success, else error code.
static fapi2::ReturnCode p9_sbe_chiplet_reset_assert_scan_clk(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
{
FAPI_INF("p9_sbe_chiplet_reset_assert_scan_clk: Entering ...");
fapi2::buffer<uint64_t> l_data64;
FAPI_DBG("assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1 for cumulus chip Mc chiplet");
FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_OPCG_REG1, l_data64));
l_data64.setBit<PERV_1_OPCG_REG1_SCAN_CLK_USE_EVEN>();
FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_REG1, l_data64));
FAPI_INF("p9_sbe_chiplet_reset_assert_scan_clk: Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief Setting up hang pulse counter for all parital good chiplet except for Tp
///
/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target
/// @return FAPI2_RC_SUCCESS if success, else error code.
static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt)
{
FAPI_INF("p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup: Entering ...");
fapi2::buffer<uint64_t> l_data64;
uint8_t l_attr_chipunit_pos = 0;
// Local variables
uint8_t i_reg0_val = 0xff;
uint8_t i_reg1_val = 0xff;
uint8_t i_reg2_val = 0xff;
uint8_t i_reg3_val = 0xff;
uint8_t i_reg4_val = 0xff;
uint8_t i_reg5_val = 0xff;
uint8_t i_reg6_val = 0xff;
uint32_t l_chipletID = i_target_cplt.getChipletNumber();
// MC Perv Targets || PCI Perv Targets
if((l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) || (l_chipletID >= PCI0_CHIPLET_ID
&& l_chipletID <= PCI2_CHIPLET_ID))
{
i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10;
i_reg6_val = p9SbeChipletReset::HANG_PULSE_0X10;
}
// OBUS & XBUS Perv Targets
else if((l_chipletID == XB_CHIPLET_ID) || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID))
{
i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10;
i_reg1_val = p9SbeChipletReset::HANG_PULSE_0X04;
i_reg6_val = p9SbeChipletReset::HANG_PULSE_0X10;
}
// Core Perv Target
else if(l_chipletID >= EC0_CHIPLET_ID && l_chipletID <= EC23_CHIPLET_ID)
{
i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10;
i_reg5_val = p9SbeChipletReset::HANG_PULSE_0X06;
i_reg6_val = p9SbeChipletReset::HANG_PULSE_0X10;
}
// Cache Perv Target
else if(l_chipletID >= EQ0_CHIPLET_ID && l_chipletID <= EQ5_CHIPLET_ID)
{
i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10;
i_reg1_val = p9SbeChipletReset::HANG_PULSE_0X01;
i_reg2_val = p9SbeChipletReset::HANG_PULSE_0X01;
i_reg3_val = p9SbeChipletReset::HANG_PULSE_0X04;
i_reg4_val = p9SbeChipletReset::HANG_PULSE_0X00;
i_reg5_val = p9SbeChipletReset::HANG_PULSE_0X06;
i_reg6_val = p9SbeChipletReset::HANG_PULSE_0X10;
}
// NEST Perv Target
else if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID)
{
i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10;
i_reg5_val = p9SbeChipletReset::HANG_PULSE_0X06;
i_reg6_val = p9SbeChipletReset::HANG_PULSE_0X10;
}
//Setting HANG_PULSE_0_REG register value (Setting all fields)
if (i_reg0_val != 0xff)
{
//HANG_PULSE_0_REG.HANG_PULSE_REG_0 = (i_reg0_val != 0xff) ? i_reg0_val
l_data64.insertFromRight<PERV_1_HANG_PULSE_0_REG_0, PERV_1_HANG_PULSE_0_REG_0_LEN>(i_reg0_val);
//HANG_PULSE_0_REG.SUPPRESS_HANG_0 = (i_reg0_val != 0xff) ? 0
l_data64.clearBit<PERV_1_HANG_PULSE_0_REG_SUPPRESS>();
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_0_REG, l_data64));
}
//Setting HANG_PULSE_1_REG register value (Setting all fields)
if (i_reg1_val != 0xff)
{
//HANG_PULSE_1_REG.HANG_PULSE_REG_1 = (i_reg1_val != 0xff) ? i_reg1_val
l_data64.insertFromRight<PERV_1_HANG_PULSE_1_REG_1, PERV_1_HANG_PULSE_1_REG_1_LEN>(i_reg1_val);
//HANG_PULSE_1_REG.SUPPRESS_HANG_1 = (i_reg1_val != 0xff) ? 0
l_data64.clearBit<PERV_1_HANG_PULSE_1_REG_SUPPRESS>();
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64));
}
//Setting HANG_PULSE_2_REG register value (Setting all fields)
if (i_reg2_val != 0xff)
{
//HANG_PULSE_2_REG.HANG_PULSE_REG_2 = (i_reg2_val != 0xff) ? i_reg2_val
l_data64.insertFromRight<PERV_1_HANG_PULSE_2_REG_2, PERV_1_HANG_PULSE_2_REG_2_LEN>(i_reg2_val);
//HANG_PULSE_2_REG.SUPPRESS_HANG_2 = (i_reg2_val != 0xff) ? 0
l_data64.clearBit<PERV_1_HANG_PULSE_2_REG_SUPPRESS>();
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64));
}
//Setting HANG_PULSE_3_REG register value (Setting all fields)
if (i_reg3_val != 0xff)
{
//HANG_PULSE_3_REG.HANG_PULSE_REG_3 = (i_reg3_val != 0xff) ? i_reg3_val
l_data64.insertFromRight<PERV_1_HANG_PULSE_3_REG_3, PERV_1_HANG_PULSE_3_REG_3_LEN>(i_reg3_val);
//HANG_PULSE_3_REG.SUPPRESS_HANG_3 = (i_reg3_val != 0xff) ? 0
l_data64.clearBit<PERV_1_HANG_PULSE_3_REG_SUPPRESS>();
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64));
}
//Setting HANG_PULSE_4_REG register value (Setting all fields)
if (i_reg4_val != 0xff)
{
//HANG_PULSE_4_REG.HANG_PULSE_REG_4 = (i_reg4_val != 0xff) ? i_reg4_val
l_data64.insertFromRight<PERV_1_HANG_PULSE_4_REG_4, PERV_1_HANG_PULSE_4_REG_4_LEN>(i_reg4_val);
//HANG_PULSE_4_REG.SUPPRESS_HANG_4 = (i_reg4_val != 0xff) ? 0
l_data64.clearBit<PERV_1_HANG_PULSE_4_REG_SUPPRESS>();
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_4_REG, l_data64));
}
//Setting HANG_PULSE_5_REG register value (Setting all fields)
if (i_reg5_val != 0xff)
{
//HANG_PULSE_5_REG.HANG_PULSE_REG_5 = (i_reg5_val != 0xff) ? i_reg5_val
l_data64.insertFromRight<PERV_1_HANG_PULSE_5_REG_5, PERV_1_HANG_PULSE_5_REG_5_LEN>(i_reg5_val);
//HANG_PULSE_5_REG.SUPPRESS_HANG_5 = (i_reg5_val != 0xff) ? 0
l_data64.clearBit<PERV_1_HANG_PULSE_5_REG_SUPPRESS>();
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_5_REG, l_data64));
}
//Setting HANG_PULSE_6_REG register value (Setting all fields)
if (i_reg6_val != 0xff)
{
//HANG_PULSE_6_REG.HANG_PULSE_REG_6 = (i_reg6_val != 0xff) ? i_reg6_val
l_data64.insertFromRight<PERV_1_HANG_PULSE_6_REG_6, PERV_1_HANG_PULSE_6_REG_6_LEN>(i_reg6_val);
//HANG_PULSE_6_REG.SUPPRESS_HANG_6 = (i_reg6_val != 0xff) ? 0
l_data64.clearBit<PERV_1_HANG_PULSE_6_REG_SUPPRESS>();
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_6_REG, l_data64));
}
// Core Perv Target
if(l_chipletID >= EC0_CHIPLET_ID && l_chipletID <= EC23_CHIPLET_ID)
{
//Setting HANG_PULSE_1_REG register value (Setting all fields)
//HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X1A
l_data64.insertFromRight<PERV_1_HANG_PULSE_1_REG_1, PERV_1_HANG_PULSE_1_REG_1_LEN>(p9SbeChipletReset::HANG_PULSE_0X1A);
l_data64.setBit<PERV_1_HANG_PULSE_1_REG_SUPPRESS>(); //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64));
}
// NEST Perv Target
if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID)
{
// Collecting partial good and chiplet unit position attribute
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_cplt,
l_attr_chipunit_pos));
if ( l_attr_chipunit_pos == N0_CHIPLET_ID )
{
//Setting HANG_PULSE_1_REG register value (Setting all fields)
//HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X18
l_data64.insertFromRight<PERV_1_HANG_PULSE_1_REG_1, PERV_1_HANG_PULSE_1_REG_1_LEN>(p9SbeChipletReset::HANG_PULSE_0X18);
l_data64.setBit<PERV_1_HANG_PULSE_1_REG_SUPPRESS>(); //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64));
//Setting HANG_PULSE_2_REG register value (Setting all fields)
//HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X22
l_data64.insertFromRight<PERV_1_HANG_PULSE_2_REG_2, PERV_1_HANG_PULSE_2_REG_2_LEN>(p9SbeChipletReset::HANG_PULSE_0X22);
l_data64.setBit<PERV_1_HANG_PULSE_2_REG_SUPPRESS>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64));
//Setting HANG_PULSE_3_REG register value (Setting all fields)
//HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X12
l_data64.insertFromRight<PERV_1_HANG_PULSE_3_REG_3, PERV_1_HANG_PULSE_3_REG_3_LEN>(p9SbeChipletReset::HANG_PULSE_0X12);
l_data64.setBit<PERV_1_HANG_PULSE_3_REG_SUPPRESS>(); //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64));
}
else if ( l_attr_chipunit_pos == N1_CHIPLET_ID )
{
//Setting HANG_PULSE_2_REG register value (Setting all fields)
//HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X0F
l_data64.insertFromRight<PERV_1_HANG_PULSE_2_REG_2, PERV_1_HANG_PULSE_2_REG_2_LEN>(p9SbeChipletReset::HANG_PULSE_0X0F);
l_data64.setBit<PERV_1_HANG_PULSE_2_REG_SUPPRESS>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64));
}
else if ( l_attr_chipunit_pos == N2_CHIPLET_ID )
{
//Setting HANG_PULSE_3_REG register value (Setting all fields)
//HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X12
l_data64.insertFromRight<PERV_1_HANG_PULSE_3_REG_3, PERV_1_HANG_PULSE_3_REG_3_LEN>(p9SbeChipletReset::HANG_PULSE_0X12);
l_data64.setBit<PERV_1_HANG_PULSE_3_REG_SUPPRESS>(); //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64));
}
else if ( l_attr_chipunit_pos == N3_CHIPLET_ID )
{
//Setting HANG_PULSE_1_REG register value (Setting all fields)
//HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X17
l_data64.insertFromRight<PERV_1_HANG_PULSE_1_REG_1, PERV_1_HANG_PULSE_1_REG_1_LEN>(p9SbeChipletReset::HANG_PULSE_0X17);
l_data64.setBit<PERV_1_HANG_PULSE_1_REG_SUPPRESS>(); //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64));
//Setting HANG_PULSE_2_REG register value (Setting all fields)
//HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X0F
l_data64.insertFromRight<PERV_1_HANG_PULSE_2_REG_2, PERV_1_HANG_PULSE_2_REG_2_LEN>(p9SbeChipletReset::HANG_PULSE_0X0F);
l_data64.setBit<PERV_1_HANG_PULSE_2_REG_SUPPRESS>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64));
//Setting HANG_PULSE_3_REG register value (Setting all fields)
//HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X13
l_data64.insertFromRight<PERV_1_HANG_PULSE_3_REG_3, PERV_1_HANG_PULSE_3_REG_3_LEN>(p9SbeChipletReset::HANG_PULSE_0X13);
l_data64.setBit<PERV_1_HANG_PULSE_3_REG_SUPPRESS>(); //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64));
//Setting HANG_PULSE_4_REG register value (Setting all fields)
//HANG_PULSE_4_REG.HANG_PULSE_REG_4 = p9SbeChipletReset::HANG_PULSE_0X1C
l_data64.insertFromRight<PERV_1_HANG_PULSE_4_REG_4, PERV_1_HANG_PULSE_4_REG_4_LEN>(p9SbeChipletReset::HANG_PULSE_0X1C);
l_data64.setBit<PERV_1_HANG_PULSE_4_REG_SUPPRESS>(); //HANG_PULSE_4_REG.SUPPRESS_HANG_4 = 1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_4_REG, l_data64));
}
}
FAPI_INF("p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup: Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief Configuring NET control registers into Default required value
///
/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target
/// @return FAPI2_RC_SUCCESS if success, else error code.
static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_net_cntl_setup(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt)
{
fapi2::buffer<uint8_t> l_read_attr;
FAPI_INF("p9_sbe_chiplet_reset_all_cplt_net_cntl_setup: Entering ...");
//Setting NET_CTRL0 register value
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
i_target_cplt.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
FAPI_DBG("Disable local clock gating VITAL");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING,
l_chip, l_read_attr));
if (l_read_attr)
{
//NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0,
p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1));
}
else
{
//NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0,
p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE));
}
//Setting NET_CTRL1 register value
//NET_CTRL1 = p9SbeChipletReset::NET_CNTL1_HW_INIT_VALUE
FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL1,
p9SbeChipletReset::NET_CNTL1_HW_INIT_VALUE));
FAPI_INF("p9_sbe_chiplet_reset_all_cplt_net_cntl_setup:Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief clock mux settings for Mc/Xbus chiplet
///
/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target
/// @param[in] i_clk_mux_value clock mux value
/// @return FAPI2_RC_SUCCESS if success, else error code.
static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_MC_XBUS(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
const fapi2::buffer<uint32_t> i_clk_mux_value)
{
fapi2::buffer<uint64_t> l_data64;
FAPI_INF("p9_sbe_chiplet_reset_clk_mux_MC_XBUS: Entering ...");
uint32_t l_chipletID = i_target_chiplet.getChipletNumber();
//Setting NET_CTRL1 register value
FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
//NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<3>()
if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) //MC
{
l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<3>());
}
else // XBUS
{
l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<8>());
}
FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
FAPI_INF("p9_sbe_chiplet_reset_clk_mux_MC_XBUS: Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief clock mux settings for OB chiplet
///
///
/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target
/// @param[in] i_clk_mux_value Clock mux value
/// @return FAPI2_RC_SUCCESS if success, else error code.
static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_obus(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
const fapi2::buffer<uint32_t> i_clk_mux_value)
{
uint8_t l_attr_unit_pos = 0;
fapi2::buffer<uint64_t> l_data64;
FAPI_INF("p9_sbe_chiplet_reset_clk_mux_obus: Entering ...");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet,
l_attr_unit_pos));
FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
if ( l_attr_unit_pos == OB0_CHIPLET_ID )
{
//Setting NET_CTRL1 register value
//NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<6>()
l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<6>());
l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>
(i_clk_mux_value.getBit<13>()); //NET_CTRL1.REFCLK_CLKMUX0_SEL = i_clk_mux_value.getBit<13>()
l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL>
(i_clk_mux_value.getBit<15>()); //NET_CTRL1.REFCLK_CLKMUX1_SEL = i_clk_mux_value.getBit<15>()
}
else if ( l_attr_unit_pos == OB1_CHIPLET_ID )
{
//Setting NET_CTRL1 register value
l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>
(i_clk_mux_value.getBit<16>()); //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<16>()
}
else if ( l_attr_unit_pos == OB2_CHIPLET_ID )
{
//Setting NET_CTRL1 register value
l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>
(i_clk_mux_value.getBit<17>()); //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<17>()
}
else if ( l_attr_unit_pos == OB3_CHIPLET_ID )
{
//Setting NET_CTRL1 register value
//NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<7>()
l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<7>());
l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>
(i_clk_mux_value.getBit<9>()); //NET_CTRL1.REFCLK_CLKMUX0_SEL = i_clk_mux_value.getBit<9>()
l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL>
(i_clk_mux_value.getBit<14>()); //NET_CTRL1.REFCLK_CLKMUX1_SEL = i_clk_mux_value.getBit<14>()
}
FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
FAPI_INF("p9_sbe_chiplet_reset_clk_mux_obus: Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief clock mux settings for Pcie chiplet
///
///
/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target
/// @param[in] i_clk_mux_value clock mux value
/// @return FAPI2_RC_SUCCESS if success, else error code.
static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
const fapi2::buffer<uint32_t> i_clk_mux_value)
{
uint8_t l_attr_unit_pos = 0;
uint8_t l_use_ss_pll = 0;
fapi2::buffer<uint64_t> l_data64;
FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Entering ...");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet,
l_attr_unit_pos),
"Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)");
// leverage SS filter PLL to feed PCI PLLs, instead of IO filter PLL
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE,
i_target_chiplet.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(),
l_use_ss_pll),
"Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE)");
if (l_use_ss_pll)
{
fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK_Type l_slow_ref_clock;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK,
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
l_slow_ref_clock),
"Error from FAPI_ATTR_GET (ATTR_DD1_SLOW_PCI_REF_CLOCK)");
if (l_slow_ref_clock != fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_SLOW)
{
l_use_ss_pll = 0;
}
}
if ( l_attr_unit_pos != 0x0E )
{
//Setting NET_CTRL1 register value
FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
if (l_use_ss_pll)
{
l_data64.clearBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>();
}
else
{
l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>((l_attr_unit_pos == 0x0D) ?
i_clk_mux_value.getBit<5>() :
i_clk_mux_value.getBit<4>()); //NET_CTRL1.PLL_CLKIN_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<5>() : i_clk_mux_value.getBit<4>()
}
if (l_attr_unit_pos == 0x0D)
{
if (l_use_ss_pll)
{
l_data64.setBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>();
}
else
{
l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>
(i_clk_mux_value.getBit<10>()); //NET_CTRL1.REFCLK_CLKMUX0_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<10>()
}
l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL>
(i_clk_mux_value.getBit<11>()); //NET_CTRL1.REFCLK_CLKMUX1_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<11>()
}
FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
}
FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief Drop clk div bypass for Mc chiplet
///
/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target
/// @return FAPI2_RC_SUCCESS if success, else error code.
static fapi2::ReturnCode p9_sbe_chiplet_reset_div_clk_bypass(
const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
{
fapi2::buffer<uint64_t> l_data64;
FAPI_INF("p9_sbe_chiplet_reset_div_clk_bypass: Entering ...");
FAPI_DBG("drop clk_div_bypass_en");
//Setting NET_CTRL1 register value
l_data64.flush<1>();
//NET_CTRL1.CLK_DIV_BYPASS_EN = 0
l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DIV_BYPASS_EN>();
FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64));
FAPI_INF("p9_sbe_chiplet_reset_div_clk_bypass: Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief Enable listen_to_sync mode for all chiplets except MC
///