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p9a_misc_scom_addresses.H
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p9a_misc_scom_addresses.H
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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/common/include/p9a_misc_scom_addresses.H $ */
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file p9a_misc_scom_addresses.H
/// @brief Defines constants for scom addresses
///
// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: SOA
// *HWP Level: 1
// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
/*---------------------------------------------------------------
*
*---------------------------------------------------------------
*
* Issues:
*
* Closed
* TOD reg same address. HW323439
* - Issue was closed with the explaination "same as p8"
* IO0 registers need fixed. HW320437
* PHB registers need fixed. HW320416 ( all regs commented out now )
* OSC/perv regs same address. HW323437
* MC regs with same address. HW323435 (matteo)
* Duplicate IOM registers. HW320456 (designers)
* PEC Sat_id issue HW329652
* PB.PB_PPE registers need fixed. HW320435
* EX05 registers need fixed. HW320427 (9020) - L2 ring id's are incorrect
* IOFPPE registers need fixed. HW320424 (9020) - Investigate NULL scope
* PEC addresses are wrong. HW322598 (9020)
* MC registers need fixed. HW320433
* VA.VA_NORTH registers need fixed. HW320436
*
* Format:
*
* <UNIT>_<SUBUNIT>_<INSTANCE>_<REGISTER>_<ACCESS/TYPE>
*
* Notes: Subunits are only added to make names unique when
* there are name collisions.
* Only units with more than one instance has instance numbers.
* If there is only one, the instance number is omitted.
*
* Instance numbers are chiplet id's for the PERV unit. The
* chiplet id's are mapped to their name and used instead of
* instance numbers. See bellow.
*
* For registers with a single access type the type and access
* methods are omitted.
*
* For access types where all bits have the same access methods, the
* access method is appended to the name. If the access methods
* are different for some bits, the access type is appended to the
* name _SCOM instead of _RO. The _RW(X) access method is omitted
* and assumed to be default.
*
* Valid units / subunits
* PU : No unit chip level
* MCD0[0..1] : mcd subunit
* PIB2OPB[0..1] : PIB2OPB subunit
* OTPROM[0..1] : otprom subunit
* NPU : common npu subunit
* NPU[0..2] : Npu stacks 0 to 2
* CTL : Npu CTL subunit
* DAT : Npu DAT subunit
* SM[0..3] : Npu SM subunits
* NTL[0..1] : Npu NTL subunit
* PERV : Pervasive
* FSI2PIB : subunit
* FSISHIFT : subunit
* FSII2C : subunit
* FSB : subunit
* EX : Ex unit (1/2 quad, 2 cores)
* L2 : L2 subunit
* L3 : L3 subunit
* PEC : PCI Pec unit
* STACK0 : subunit
* STACK1 : subunit
* STACK2 : subunit
* C : core
* EQ : quad
* OBUS : obus
* CAPP : capp
* MCBIST : mcbist
* MCA : mca
* NVBUS : (not implemented yet)
* PHB : (not implemented yet)
* MI : (not implemented yet)
* DMI : (not implemented yet)
* MCS : (not implemented yet)
* OCC : (not implemented yet)
* PPE : (not implemented yet)
* SBE : (not implemented yet)
* XBUS : (not implemented yet)
*
* Pervasive instance names follow chiplet id.
*
* Instance/ | Chiplet
* Chiplet | name
* -----------+-----------
* 0x00 | PIB
* 0x01 | TP
* 0x02 | N0
* 0x03 | N1
* 0x04 | N2
* 0x05 | N3
* 0x06 | XB
* 0x07 | MC01
* 0x08 | MC23
* 0x09 | OB0
* 0x0A | OB1
* 0x0B | OB2
* 0x0C | OB3
* 0x0D | PCI0
* 0x0E | PCI1
* 0x0F | PCI2
* 0x10 | EP00
* 0x11 | EP01
* 0x12 | EP02
* 0x13 | EP03
* 0x14 | EP04
* 0x15 | EP05
* 0x20 | EC00
* 0x21 | EC01
* 0x22 | EC02
* 0x23 | EC03
* 0x24 | EC04
* 0x25 | EC05
* 0x26 | EC06
* 0x27 | EC07
* 0x28 | EC08
* 0x29 | EC09
* 0x2A | EC10
* 0x2B | EC11
* 0x2C | EC12
* 0x2D | EC13
* 0x2E | EC14
* 0x2F | EC15
* 0x30 | EC16
* 0x31 | EC17
* 0x32 | EC18
* 0x33 | EC19
* 0x34 | EC20
* 0x35 | EC21
* 0x36 | EC22
* 0x37 | EC23
*
*
*---------------------------------------------------------------
*
* NOTES:
*
* there is a SPR ring that goes around the chip with an
* address(0:9)/tid(0:1) (thread id)/mfspr_data(0:63) and return mfspr_data_v/mfspr_data(0:63)
*
* Add PU_<SUBUNITS> (only if there are conflicts on these registers)
* 0x0001XXXX OTPROM
* 0x0002XXXX FSIM0
* 0x0003XXXX FSIM1
* 0x0004XXXX TOD
* 0x0005XXXX FSI_MBOX
* 0x0006XXXX OCI_BRIDGE
* 0x0007XXXX SPI_ADC
* 0x0008XXXX PIBMEM
* 0x0009XXXX ADU
* 0x000AXXXX I2CM
* 0x000BXXXX SBE_FIFO
* 0x000DXXXX PSU
* 0x000EXXXX SBE
*
* 0x0000100A for FSI2PIB => PERV_FSI2PIB
* 0x00000Cxx for FSISHIFT => PERV_FSISHIFT
* 0x000018xx for FSI I2C => PERV_FSII2C
* 0x000024xx for FSI SBEFIFO => PERV_FSB
*
* 0x00000400 PEEK_TABLE
* 0x00000800 FSI_SLAVE
* 0x00000C00 FSI_SHIFT
* 0x00001000 FSI2PIB
* 0x00001400 FSI_SCRATCHPAD
* 0x00001800 FSI_I2CM
* 0x00002400 FSI_SBE_FIFO
*
* address fields
* 0xCCRPxxxx
*
* CC=chiplet
* R=always 0?
* P=port
* 0=gpregs
* 1=normal unit scom ring (exclude)
* 3=clock controller
* 4=firs
* 5=cpm
*
* =============================================================================
* Compiling
*
* Precompile the header to save time on subsquent compiles:
* g++ -I. -c scom_addresses.H
*
* Use these options to help reduce the binary size
* g++ -I. -Os -fdata-sections -ffunction-sections <file>.C -o <output> -Wl,--gc-sections
*
*
*---------------------------------------------------------------
*/
#ifndef __P9A_MISC_SCOM_ADDRESSES_H
#define __P9A_MISC_SCOM_ADDRESSES_H
static const uint64_t P9A_MI_AACR = 0x0501082Cull;
static const uint64_t P9A_MI_0_AACR = 0x0501082Cull;
static const uint64_t P9A_MI_1_AACR = 0x050108ACull;
static const uint64_t P9A_MI_2_AACR = 0x0301082Cull;
static const uint64_t P9A_MI_3_AACR = 0x030108ACull;
static const uint64_t P9A_MI_AADR = 0x0501082Dull;
static const uint64_t P9A_MI_0_AADR = 0x0501082Dull;
static const uint64_t P9A_MI_1_AADR = 0x050108ADull;
static const uint64_t P9A_MI_2_AADR = 0x0301082Dull;
static const uint64_t P9A_MI_3_AADR = 0x030108ADull;
static const uint64_t P9A_MI_AAER = 0x0501082Eull;
static const uint64_t P9A_MI_0_AAER = 0x0501082Eull;
static const uint64_t P9A_MI_1_AAER = 0x050108AEull;
static const uint64_t P9A_MI_2_AAER = 0x0301082Eull;
static const uint64_t P9A_MI_3_AAER = 0x030108AEull;
static const uint64_t P9A_PHB_ACT0_REG = 0x0D01090Eull;
static const uint64_t P9A_PHB_0_ACT0_REG = 0x0D01090Eull;
static const uint64_t P9A_PHB_1_ACT0_REG = 0x0E01090Eull;
static const uint64_t P9A_PHB_2_ACT0_REG = 0x0E01094Eull;
static const uint64_t P9A_PHB_3_ACT0_REG = 0x0F01090Eull;
static const uint64_t P9A_PHB_4_ACT0_REG = 0x0F01094Eull;
static const uint64_t P9A_PHB_5_ACT0_REG = 0x0F01098Eull;
static const uint64_t P9A_PHB_ACTION1_REG = 0x0D01090Full;
static const uint64_t P9A_PHB_0_ACTION1_REG = 0x0D01090Full;
static const uint64_t P9A_PHB_1_ACTION1_REG = 0x0E01090Full;
static const uint64_t P9A_PHB_2_ACTION1_REG = 0x0E01094Full;
static const uint64_t P9A_PHB_3_ACTION1_REG = 0x0F01090Full;
static const uint64_t P9A_PHB_4_ACTION1_REG = 0x0F01094Full;
static const uint64_t P9A_PHB_5_ACTION1_REG = 0x0F01098Full;
static const uint64_t P9A_PEC_ADDREXTMASK_REG = 0x04010C05ull;
static const uint64_t P9A_PEC_0_ADDREXTMASK_REG = 0x04010C05ull;
static const uint64_t P9A_PEC_1_ADDREXTMASK_REG = 0x04011005ull;
static const uint64_t P9A_PEC_2_ADDREXTMASK_REG = 0x04011405ull;
static const uint64_t P9A_PU_ADDR_0_HASH_FUNCTION_REG = 0x02011141ull;
static const uint64_t P9A_PU_ADDR_10_HASH_FUNCTION_REG = 0x0201114Bull;
static const uint64_t P9A_PU_ADDR_1_HASH_FUNCTION_REG = 0x02011142ull;
static const uint64_t P9A_PU_ADDR_2_HASH_FUNCTION_REG = 0x02011143ull;
static const uint64_t P9A_PU_ADDR_3_HASH_FUNCTION_REG = 0x02011144ull;
static const uint64_t P9A_PU_ADDR_4_HASH_FUNCTION_REG = 0x02011145ull;
static const uint64_t P9A_PU_ADDR_5_HASH_FUNCTION_REG = 0x02011146ull;
static const uint64_t P9A_PU_ADDR_6_HASH_FUNCTION_REG = 0x02011147ull;
static const uint64_t P9A_PU_ADDR_7_HASH_FUNCTION_REG = 0x02011148ull;
static const uint64_t P9A_PU_ADDR_8_HASH_FUNCTION_REG = 0x02011149ull;
static const uint64_t P9A_PU_ADDR_9_HASH_FUNCTION_REG = 0x0201114Aull;
static const uint64_t P9A_PU_ADS_XSCOM_CMD_REG = 0x0009001Cull;
static const uint64_t P9A_PU_ADU_HANG_DIV_REG = 0x00090050ull;
static const uint64_t P9A_PU_ALTD_ADDR_REG = 0x00090000ull;
static const uint64_t P9A_PU_ALTD_CMD_REG = 0x00090001ull;
static const uint64_t P9A_PU_ALTD_DATA_REG = 0x00090004ull;
static const uint64_t P9A_PU_ALTD_OPTION_REG = 0x00090002ull;
static const uint64_t P9A_PU_ALTD_STATUS_REG = 0x00090003ull;
static const uint64_t P9A_PU_ALTER_CREDIT_COUNTERS = 0x03011E30ull;
//DUPS: 03011E30,
static const uint64_t P9A_PU_NPU2_SM1_ALTER_CREDIT_COUNTERS = 0x05011230ull;
static const uint64_t P9A_PU_NPU2_SM3_ALTER_CREDIT_COUNTERS = 0x05011260ull;
static const uint64_t P9A__SM1_ALTER_CREDIT_COUNTERS = 0x05011630ull;
static const uint64_t P9A__SM3_ALTER_CREDIT_COUNTERS = 0x05011660ull;
static const uint64_t P9A_CAPP_APCFG = 0x02010819ull;
static const uint64_t P9A_CAPP_0_APCFG = 0x02010819ull;
static const uint64_t P9A_CAPP_APCLCO = 0x02010821ull;
static const uint64_t P9A_CAPP_0_APCLCO = 0x02010821ull;
static const uint64_t P9A_CAPP_APCRDFSMMASK = 0x02010823ull;
static const uint64_t P9A_CAPP_0_APCRDFSMMASK = 0x02010823ull;
static const uint64_t P9A_CAPP_APCTL = 0x02010818ull;
static const uint64_t P9A_CAPP_0_APCTL = 0x02010818ull;
static const uint64_t P9A_CAPP_APC_ARRY_ADDR = 0x0201082Aull;
static const uint64_t P9A_CAPP_0_APC_ARRY_ADDR = 0x0201082Aull;
static const uint64_t P9A_CAPP_APC_ARRY_RDDATA = 0x0201082Bull;
static const uint64_t P9A_CAPP_0_APC_ARRY_RDDATA = 0x0201082Bull;
static const uint64_t P9A_CAPP_APC_ARRY_WRDATA = 0x02010842ull;
static const uint64_t P9A_CAPP_0_APC_ARRY_WRDATA = 0x02010842ull;
static const uint64_t P9A_CAPP_APC_ERRINJ = 0x02010810ull;
static const uint64_t P9A_CAPP_0_APC_ERRINJ = 0x02010810ull;
static const uint64_t P9A_CAPP_APC_PMUSEL = 0x02010816ull;
static const uint64_t P9A_CAPP_0_APC_PMUSEL = 0x02010816ull;
static const uint64_t P9A_CAPP_ASE_TUPLE0 = 0x02010846ull;
static const uint64_t P9A_CAPP_0_ASE_TUPLE0 = 0x02010846ull;
static const uint64_t P9A_CAPP_ASE_TUPLE1 = 0x02010847ull;
static const uint64_t P9A_CAPP_0_ASE_TUPLE1 = 0x02010847ull;
static const uint64_t P9A_CAPP_ASE_TUPLE2 = 0x02010848ull;
static const uint64_t P9A_CAPP_0_ASE_TUPLE2 = 0x02010848ull;
static const uint64_t P9A_CAPP_ASE_TUPLE3 = 0x02010849ull;
static const uint64_t P9A_CAPP_0_ASE_TUPLE3 = 0x02010849ull;
static const uint64_t P9A_PEC_ASSIST_INTERRUPT_REG = 0x0D0F0011ull;
static const uint64_t P9A_PEC_0_ASSIST_INTERRUPT_REG = 0x0D0F0011ull;
static const uint64_t P9A_PEC_1_ASSIST_INTERRUPT_REG = 0x0E0F0011ull;
static const uint64_t P9A_PEC_2_ASSIST_INTERRUPT_REG = 0x0F0F0011ull;
static const uint64_t P9A_PEC_ATOMIC_LOCK_REG = 0x0D0F03FFull;
static const uint64_t P9A_PEC_0_ATOMIC_LOCK_REG = 0x0D0F03FFull;
static const uint64_t P9A_PEC_1_ATOMIC_LOCK_REG = 0x0E0F03FFull;
static const uint64_t P9A_PEC_2_ATOMIC_LOCK_REG = 0x0F0F03FFull;
static const uint64_t P9A_PU_ATR_HA_PTR = 0x03011FF2ull;
//DUPS: 03011FD2, 03011E12, 03011DF2,
static const uint64_t P9A_PU_NPU1_NTL1_ATR_HA_PTR = 0x050111F2ull;
static const uint64_t P9A_PU_NPU2_SM0_ATR_HA_PTR = 0x05011212ull;
static const uint64_t P9A_PU_NPU_NTL0_ATR_HA_PTR = 0x050113D2ull;
//DUPS: 050117D2,
static const uint64_t P9A_PU_NPU_NTL1_ATR_HA_PTR = 0x050113F2ull;
//DUPS: 050117F2,
static const uint64_t P9A__NTL1_ATR_HA_PTR = 0x050115F2ull;
static const uint64_t P9A__SM0_ATR_HA_PTR = 0x05011612ull;
static const uint64_t P9A_PU_ATS_CKSW = 0x03011EB4ull;
static const uint64_t P9A_PU_NPU2_DAT_ATS_CKSW = 0x050112B4ull;
static const uint64_t P9A__DAT_ATS_CKSW = 0x050116B4ull;
static const uint64_t P9A_PU_ATS_CTRL = 0x03011ED0ull;
static const uint64_t P9A_PU_NPU2_NTL0_ATS_CTRL = 0x050112D0ull;
static const uint64_t P9A__NTL0_ATS_CTRL = 0x050116D0ull;
static const uint64_t P9A_PU_ATS_HOLD = 0x03011EB5ull;
static const uint64_t P9A_PU_NPU2_DAT_ATS_HOLD = 0x050112B5ull;
static const uint64_t P9A__DAT_ATS_HOLD = 0x050116B5ull;
static const uint64_t P9A_PU_ATS_MASK = 0x03011EB6ull;
static const uint64_t P9A_PU_NPU2_DAT_ATS_MASK = 0x050112B6ull;
static const uint64_t P9A__DAT_ATS_MASK = 0x050116B6ull;
static const uint64_t P9A_PU_ATS_TCR = 0x03011ED6ull;
static const uint64_t P9A_PU_NPU2_NTL0_ATS_TCR = 0x050112D6ull;
static const uint64_t P9A__NTL0_ATS_TCR = 0x050116D6ull;
static const uint64_t P9A_PEC_ATTN_INTERRUPT_REG = 0x0D0F001Aull;
static const uint64_t P9A_PEC_0_ATTN_INTERRUPT_REG = 0x0D0F001Aull;
static const uint64_t P9A_PEC_1_ATTN_INTERRUPT_REG = 0x0E0F001Aull;
static const uint64_t P9A_PEC_2_ATTN_INTERRUPT_REG = 0x0F0F001Aull;
static const uint64_t P9A_PU_BANK0_MCD_BOT = 0x0301140Cull;
static const uint64_t P9A_PU_MCD1_BANK0_MCD_BOT = 0x0301100Cull;
static const uint64_t P9A_PU_BANK0_MCD_CHA = 0x0301140Dull;
static const uint64_t P9A_PU_MCD1_BANK0_MCD_CHA = 0x0301100Dull;
static const uint64_t P9A_PU_BANK0_MCD_CMD = 0x0301140Eull;
static const uint64_t P9A_PU_MCD1_BANK0_MCD_CMD = 0x0301100Eull;
static const uint64_t P9A_PU_BANK0_MCD_REC = 0x03011410ull;
static const uint64_t P9A_PU_MCD1_BANK0_MCD_REC = 0x03011010ull;
static const uint64_t P9A_PU_BANK0_MCD_RW = 0x0301140Full;
static const uint64_t P9A_PU_MCD1_BANK0_MCD_RW = 0x0301100Full;
static const uint64_t P9A_PU_BANK0_MCD_STR = 0x0301140Bull;
static const uint64_t P9A_PU_MCD1_BANK0_MCD_STR = 0x0301100Bull;
static const uint64_t P9A_PU_BANK0_MCD_TOP = 0x0301140Aull;
static const uint64_t P9A_PU_MCD1_BANK0_MCD_TOP = 0x0301100Aull;
static const uint64_t P9A_PU_BANK0_MCD_VGC = 0x03011411ull;
static const uint64_t P9A_PU_MCD1_BANK0_MCD_VGC = 0x03011011ull;
static const uint64_t P9A_PU_BARE_REG = 0x040110D4ull;
static const uint64_t P9A_PHB_BARE_REG = 0x04010C54ull;
static const uint64_t P9A_PHB_0_BARE_REG = 0x04010C54ull;
static const uint64_t P9A_PHB_1_BARE_REG = 0x04011054ull;
static const uint64_t P9A_PHB_2_BARE_REG = 0x04011094ull;
static const uint64_t P9A_PHB_3_BARE_REG = 0x04011454ull;
static const uint64_t P9A_PHB_4_BARE_REG = 0x04011494ull;
static const uint64_t P9A_PHB_5_BARE_REG = 0x040114D4ull;
static const uint64_t P9A_PU_BCDE_CTL_OCI = 0xC0040080ull;
static const uint64_t P9A_PU_BCDE_CTL_PIB = 0x00068010ull;
static const uint64_t P9A_PU_BCDE_OCIBAR_OCI = 0xC00400A0ull;
static const uint64_t P9A_PU_BCDE_OCIBAR_PIB = 0x00068014ull;
static const uint64_t P9A_PU_BCDE_PBADR_OCI = 0xC0040098ull;
static const uint64_t P9A_PU_BCDE_PBADR_PIB = 0x00068013ull;
static const uint64_t P9A_PU_BCDE_SET_OCI = 0xC0040088ull;
static const uint64_t P9A_PU_BCDE_SET_PIB = 0x00068011ull;
static const uint64_t P9A_PU_BCDE_STAT_OCI = 0xC0040090ull;
static const uint64_t P9A_PU_BCDE_STAT_PIB = 0x00068012ull;
static const uint64_t P9A_PU_BCUE_CTL_OCI = 0xC00400A8ull;
static const uint64_t P9A_PU_BCUE_CTL_PIB = 0x00068015ull;
static const uint64_t P9A_PU_BCUE_OCIBAR_OCI = 0xC00400C8ull;
static const uint64_t P9A_PU_BCUE_OCIBAR_PIB = 0x00068019ull;
static const uint64_t P9A_PU_BCUE_PBADR_OCI = 0xC00400C0ull;
static const uint64_t P9A_PU_BCUE_PBADR_PIB = 0x00068018ull;
static const uint64_t P9A_PU_BCUE_SET_OCI = 0xC00400B0ull;
static const uint64_t P9A_PU_BCUE_SET_PIB = 0x00068016ull;
static const uint64_t P9A_PU_BCUE_STAT_OCI = 0xC00400B8ull;
static const uint64_t P9A_PU_BCUE_STAT_PIB = 0x00068017ull;
static const uint64_t P9A_PU_BDF2PE_0_CONFIG = 0x03011DB0ull;
//DUPS: 03011F50,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_0_CONFIG = 0x050111B0ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_0_CONFIG = 0x05011350ull;
//DUPS: 05011750,
static const uint64_t P9A__DAT_BDF2PE_0_CONFIG = 0x050115B0ull;
static const uint64_t P9A_PU_BDF2PE_10_CONFIG = 0x03011DBAull;
//DUPS: 03011F5A,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_10_CONFIG = 0x050111BAull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_10_CONFIG = 0x0501135Aull;
//DUPS: 0501175A,
static const uint64_t P9A__DAT_BDF2PE_10_CONFIG = 0x050115BAull;
static const uint64_t P9A_PU_BDF2PE_11_CONFIG = 0x03011DBBull;
//DUPS: 03011F5B,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_11_CONFIG = 0x050111BBull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_11_CONFIG = 0x0501135Bull;
//DUPS: 0501175B,
static const uint64_t P9A__DAT_BDF2PE_11_CONFIG = 0x050115BBull;
static const uint64_t P9A_PU_BDF2PE_12_CONFIG = 0x03011DBCull;
//DUPS: 03011F5C,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_12_CONFIG = 0x050111BCull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_12_CONFIG = 0x0501135Cull;
//DUPS: 0501175C,
static const uint64_t P9A__DAT_BDF2PE_12_CONFIG = 0x050115BCull;
static const uint64_t P9A_PU_BDF2PE_13_CONFIG = 0x03011DBDull;
//DUPS: 03011F5D,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_13_CONFIG = 0x050111BDull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_13_CONFIG = 0x0501135Dull;
//DUPS: 0501175D,
static const uint64_t P9A__DAT_BDF2PE_13_CONFIG = 0x050115BDull;
static const uint64_t P9A_PU_BDF2PE_14_CONFIG = 0x03011DBEull;
//DUPS: 03011F5E,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_14_CONFIG = 0x050111BEull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_14_CONFIG = 0x0501135Eull;
//DUPS: 0501175E,
static const uint64_t P9A__DAT_BDF2PE_14_CONFIG = 0x050115BEull;
static const uint64_t P9A_PU_BDF2PE_15_CONFIG = 0x03011DBFull;
//DUPS: 03011F5F,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_15_CONFIG = 0x050111BFull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_15_CONFIG = 0x0501135Full;
//DUPS: 0501175F,
static const uint64_t P9A__DAT_BDF2PE_15_CONFIG = 0x050115BFull;
static const uint64_t P9A_PU_BDF2PE_1_CONFIG = 0x03011DB1ull;
//DUPS: 03011F51,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_1_CONFIG = 0x050111B1ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_1_CONFIG = 0x05011351ull;
//DUPS: 05011751,
static const uint64_t P9A__DAT_BDF2PE_1_CONFIG = 0x050115B1ull;
static const uint64_t P9A_PU_BDF2PE_2_CONFIG = 0x03011DB2ull;
//DUPS: 03011F52,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_2_CONFIG = 0x050111B2ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_2_CONFIG = 0x05011352ull;
//DUPS: 05011752,
static const uint64_t P9A__DAT_BDF2PE_2_CONFIG = 0x050115B2ull;
static const uint64_t P9A_PU_BDF2PE_3_CONFIG = 0x03011DB3ull;
//DUPS: 03011F53,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_3_CONFIG = 0x050111B3ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_3_CONFIG = 0x05011353ull;
//DUPS: 05011753,
static const uint64_t P9A__DAT_BDF2PE_3_CONFIG = 0x050115B3ull;
static const uint64_t P9A_PU_BDF2PE_4_CONFIG = 0x03011DB4ull;
//DUPS: 03011F54,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_4_CONFIG = 0x050111B4ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_4_CONFIG = 0x05011354ull;
//DUPS: 05011754,
static const uint64_t P9A__DAT_BDF2PE_4_CONFIG = 0x050115B4ull;
static const uint64_t P9A_PU_BDF2PE_5_CONFIG = 0x03011DB5ull;
//DUPS: 03011F55,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_5_CONFIG = 0x050111B5ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_5_CONFIG = 0x05011355ull;
//DUPS: 05011755,
static const uint64_t P9A__DAT_BDF2PE_5_CONFIG = 0x050115B5ull;
static const uint64_t P9A_PU_BDF2PE_6_CONFIG = 0x03011DB6ull;
//DUPS: 03011F56,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_6_CONFIG = 0x050111B6ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_6_CONFIG = 0x05011356ull;
//DUPS: 05011756,
static const uint64_t P9A__DAT_BDF2PE_6_CONFIG = 0x050115B6ull;
static const uint64_t P9A_PU_BDF2PE_7_CONFIG = 0x03011DB7ull;
//DUPS: 03011F57,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_7_CONFIG = 0x050111B7ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_7_CONFIG = 0x05011357ull;
//DUPS: 05011757,
static const uint64_t P9A__DAT_BDF2PE_7_CONFIG = 0x050115B7ull;
static const uint64_t P9A_PU_BDF2PE_8_CONFIG = 0x03011DB8ull;
//DUPS: 03011F58,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_8_CONFIG = 0x050111B8ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_8_CONFIG = 0x05011358ull;
//DUPS: 05011758,
static const uint64_t P9A__DAT_BDF2PE_8_CONFIG = 0x050115B8ull;
static const uint64_t P9A_PU_BDF2PE_9_CONFIG = 0x03011DB9ull;
//DUPS: 03011F59,
static const uint64_t P9A_PU_NPU1_DAT_BDF2PE_9_CONFIG = 0x050111B9ull;
static const uint64_t P9A_PU_NPU_SM2_BDF2PE_9_CONFIG = 0x05011359ull;
//DUPS: 05011759,
static const uint64_t P9A__DAT_BDF2PE_9_CONFIG = 0x050115B9ull;
static const uint64_t P9A_PEC_BIST = 0x0D03000Bull;
static const uint64_t P9A_PEC_0_BIST = 0x0D03000Bull;
static const uint64_t P9A_PEC_1_BIST = 0x0E03000Bull;
static const uint64_t P9A_PEC_2_BIST = 0x0F03000Bull;
static const uint64_t P9A_CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL = 0x0201082Cull;
static const uint64_t P9A_CAPP_0_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL = 0x0201082Cull;
static const uint64_t P9A_CAPP_CAPP_ERR_STATUS_CONTROL = 0x0201080Eull;
static const uint64_t P9A_CAPP_0_CAPP_ERR_STATUS_CONTROL = 0x0201080Eull;
static const uint64_t P9A_PEC_CC_ATOMIC_LOCK_REG = 0x0D0303FFull;
static const uint64_t P9A_PEC_0_CC_ATOMIC_LOCK_REG = 0x0D0303FFull;
static const uint64_t P9A_PEC_1_CC_ATOMIC_LOCK_REG = 0x0E0303FFull;
static const uint64_t P9A_PEC_2_CC_ATOMIC_LOCK_REG = 0x0F0303FFull;
static const uint64_t P9A_PEC_CC_PROTECT_MODE_REG = 0x0D0303FEull;
static const uint64_t P9A_PEC_0_CC_PROTECT_MODE_REG = 0x0D0303FEull;
static const uint64_t P9A_PEC_1_CC_PROTECT_MODE_REG = 0x0E0303FEull;
static const uint64_t P9A_PEC_2_CC_PROTECT_MODE_REG = 0x0F0303FEull;
static const uint64_t P9A_PU_CERR_ECC_FIRST = 0x03011DC6ull;
static const uint64_t P9A_PU_NPU1_NTL0_CERR_ECC_FIRST = 0x050111C6ull;
static const uint64_t P9A__NTL0_CERR_ECC_FIRST = 0x050115C6ull;
static const uint64_t P9A_PU_CERR_ECC_HOLD = 0x03011DC4ull;
static const uint64_t P9A_PU_NPU1_NTL0_CERR_ECC_HOLD = 0x050111C4ull;
static const uint64_t P9A__NTL0_CERR_ECC_HOLD = 0x050115C4ull;
static const uint64_t P9A_PU_CERR_ECC_MASK = 0x03011DC5ull;
static const uint64_t P9A_PU_NPU1_NTL0_CERR_ECC_MASK = 0x050111C5ull;
static const uint64_t P9A__NTL0_CERR_ECC_MASK = 0x050115C5ull;
static const uint64_t P9A_PU_CERR_FIRST0 = 0x03011D73ull;
//DUPS: 03011D2F, 03011C53, 03011C0F, 03011CB3, 03011C6F, 03011D13, 03011CCF, 03011D9B,
static const uint64_t P9A_PU_NPU0_DAT_CERR_FIRST0 = 0x050110B3ull;
static const uint64_t P9A_PU_NPU1_CTL_CERR_FIRST0 = 0x0501119Bull;
static const uint64_t P9A_PU_NPU0_NTL0_CERR_FIRST0 = 0x050110CFull;
static const uint64_t P9A_PU_NPU0_SM0_CERR_FIRST0 = 0x0501100Full;
static const uint64_t P9A_PU_NPU0_SM2_CERR_FIRST0 = 0x05011053ull;
static const uint64_t P9A_PU_NPU0_SM3_CERR_FIRST0 = 0x0501106Full;
static const uint64_t P9A_PU_NPU1_SM0_CERR_FIRST0 = 0x05011113ull;
static const uint64_t P9A_PU_NPU1_SM1_CERR_FIRST0 = 0x0501112Full;
static const uint64_t P9A_PU_NPU1_SM3_CERR_FIRST0 = 0x05011173ull;
static const uint64_t P9A_PU_NPU_MSC_DAT_CERR_FIRST0 = 0x050114B3ull;
static const uint64_t P9A_PU_NPU_MSC_NTL0_CERR_FIRST0 = 0x050114CFull;
static const uint64_t P9A_PU_NPU_MSC_SM0_CERR_FIRST0 = 0x0501140Full;
static const uint64_t P9A_PU_NPU_MSC_SM2_CERR_FIRST0 = 0x05011453ull;
static const uint64_t P9A_PU_NPU_MSC_SM3_CERR_FIRST0 = 0x0501146Full;
static const uint64_t P9A__CTL_CERR_FIRST0 = 0x0501159Bull;
static const uint64_t P9A__SM0_CERR_FIRST0 = 0x05011513ull;
static const uint64_t P9A__SM1_CERR_FIRST0 = 0x0501152Full;
static const uint64_t P9A__SM3_CERR_FIRST0 = 0x05011573ull;
static const uint64_t P9A_PU_CERR_FIRST1 = 0x03011D30ull;
//DUPS: 03011C10, 03011C70, 03011CD0, 03011D9C, 03011FE4, 03011FC4, 03011E04, 03011DE4,
static const uint64_t P9A_PU_NPU1_CTL_CERR_FIRST1 = 0x0501119Cull;
static const uint64_t P9A_PU_NPU0_NTL0_CERR_FIRST1 = 0x050110D0ull;
static const uint64_t P9A_PU_NPU0_SM0_CERR_FIRST1 = 0x05011010ull;
static const uint64_t P9A_PU_NPU0_SM3_CERR_FIRST1 = 0x05011070ull;
static const uint64_t P9A_PU_NPU1_NTL1_CERR_FIRST1 = 0x050111E4ull;
static const uint64_t P9A_PU_NPU1_SM1_CERR_FIRST1 = 0x05011130ull;
static const uint64_t P9A_PU_NPU2_SM0_CERR_FIRST1 = 0x05011204ull;
static const uint64_t P9A_PU_NPU_MSC_NTL0_CERR_FIRST1 = 0x050114D0ull;
static const uint64_t P9A_PU_NPU_MSC_SM0_CERR_FIRST1 = 0x05011410ull;
static const uint64_t P9A_PU_NPU_MSC_SM3_CERR_FIRST1 = 0x05011470ull;
static const uint64_t P9A_PU_NPU_NTL0_CERR_FIRST1 = 0x050113C4ull;
//DUPS: 050117C4,
static const uint64_t P9A_PU_NPU_NTL1_CERR_FIRST1 = 0x050113E4ull;
//DUPS: 050117E4,
static const uint64_t P9A__CTL_CERR_FIRST1 = 0x0501159Cull;
static const uint64_t P9A__NTL1_CERR_FIRST1 = 0x050115E4ull;
static const uint64_t P9A__SM0_CERR_FIRST1 = 0x05011604ull;
static const uint64_t P9A__SM1_CERR_FIRST1 = 0x05011530ull;
static const uint64_t P9A_PU_CERR_FIRST2 = 0x03011D31ull;
//DUPS: 03011C11, 03011C71, 03011CD1, 03011FE8, 03011FC8, 03011E08, 03011DE8,
static const uint64_t P9A_PU_NPU0_NTL0_CERR_FIRST2 = 0x050110D1ull;
static const uint64_t P9A_PU_NPU0_SM0_CERR_FIRST2 = 0x05011011ull;
static const uint64_t P9A_PU_NPU0_SM3_CERR_FIRST2 = 0x05011071ull;
static const uint64_t P9A_PU_NPU1_NTL1_CERR_FIRST2 = 0x050111E8ull;
static const uint64_t P9A_PU_NPU1_SM1_CERR_FIRST2 = 0x05011131ull;
static const uint64_t P9A_PU_NPU2_SM0_CERR_FIRST2 = 0x05011208ull;
static const uint64_t P9A_PU_NPU_MSC_NTL0_CERR_FIRST2 = 0x050114D1ull;
static const uint64_t P9A_PU_NPU_MSC_SM0_CERR_FIRST2 = 0x05011411ull;
static const uint64_t P9A_PU_NPU_MSC_SM3_CERR_FIRST2 = 0x05011471ull;
static const uint64_t P9A_PU_NPU_NTL0_CERR_FIRST2 = 0x050113C8ull;
//DUPS: 050117C8,
static const uint64_t P9A_PU_NPU_NTL1_CERR_FIRST2 = 0x050113E8ull;
//DUPS: 050117E8,
static const uint64_t P9A__NTL1_CERR_FIRST2 = 0x050115E8ull;
static const uint64_t P9A__SM0_CERR_FIRST2 = 0x05011608ull;
static const uint64_t P9A__SM1_CERR_FIRST2 = 0x05011531ull;
static const uint64_t P9A_PU_CERR_FIRST_MASK1 = 0x03011FE5ull;
//DUPS: 03011FC5, 03011E05, 03011DE5,
static const uint64_t P9A_PU_NPU1_NTL1_CERR_FIRST_MASK1 = 0x050111E5ull;
static const uint64_t P9A_PU_NPU2_SM0_CERR_FIRST_MASK1 = 0x05011205ull;
static const uint64_t P9A_PU_NPU_NTL0_CERR_FIRST_MASK1 = 0x050113C5ull;
//DUPS: 050117C5,
static const uint64_t P9A_PU_NPU_NTL1_CERR_FIRST_MASK1 = 0x050113E5ull;
//DUPS: 050117E5,
static const uint64_t P9A__NTL1_CERR_FIRST_MASK1 = 0x050115E5ull;
static const uint64_t P9A__SM0_CERR_FIRST_MASK1 = 0x05011605ull;
static const uint64_t P9A_PU_CERR_FIRST_MASK2 = 0x03011FE9ull;
//DUPS: 03011FC9, 03011E09, 03011DE9,
static const uint64_t P9A_PU_NPU1_NTL1_CERR_FIRST_MASK2 = 0x050111E9ull;
static const uint64_t P9A_PU_NPU2_SM0_CERR_FIRST_MASK2 = 0x05011209ull;
static const uint64_t P9A_PU_NPU_NTL0_CERR_FIRST_MASK2 = 0x050113C9ull;
//DUPS: 050117C9,
static const uint64_t P9A_PU_NPU_NTL1_CERR_FIRST_MASK2 = 0x050113E9ull;
//DUPS: 050117E9,
static const uint64_t P9A__NTL1_CERR_FIRST_MASK2 = 0x050115E9ull;
static const uint64_t P9A__SM0_CERR_FIRST_MASK2 = 0x05011609ull;
static const uint64_t P9A_PU_CERR_HOLD0 = 0x03011D75ull;
//DUPS: 03011D35, 03011C55, 03011C15, 03011CB5, 03011C75, 03011D15, 03011CD5, 03011D9F,
static const uint64_t P9A_PU_NPU0_DAT_CERR_HOLD0 = 0x050110B5ull;
static const uint64_t P9A_PU_NPU1_CTL_CERR_HOLD0 = 0x0501119Full;
static const uint64_t P9A_PU_NPU0_NTL0_CERR_HOLD0 = 0x050110D5ull;
static const uint64_t P9A_PU_NPU0_SM0_CERR_HOLD0 = 0x05011015ull;
static const uint64_t P9A_PU_NPU0_SM2_CERR_HOLD0 = 0x05011055ull;
static const uint64_t P9A_PU_NPU0_SM3_CERR_HOLD0 = 0x05011075ull;
static const uint64_t P9A_PU_NPU1_SM0_CERR_HOLD0 = 0x05011115ull;
static const uint64_t P9A_PU_NPU1_SM1_CERR_HOLD0 = 0x05011135ull;
static const uint64_t P9A_PU_NPU1_SM3_CERR_HOLD0 = 0x05011175ull;
static const uint64_t P9A_PU_NPU_MSC_DAT_CERR_HOLD0 = 0x050114B5ull;
static const uint64_t P9A_PU_NPU_MSC_NTL0_CERR_HOLD0 = 0x050114D5ull;
static const uint64_t P9A_PU_NPU_MSC_SM0_CERR_HOLD0 = 0x05011415ull;
static const uint64_t P9A_PU_NPU_MSC_SM2_CERR_HOLD0 = 0x05011455ull;
static const uint64_t P9A_PU_NPU_MSC_SM3_CERR_HOLD0 = 0x05011475ull;
static const uint64_t P9A__CTL_CERR_HOLD0 = 0x0501159Full;
static const uint64_t P9A__SM0_CERR_HOLD0 = 0x05011515ull;
static const uint64_t P9A__SM1_CERR_HOLD0 = 0x05011535ull;
static const uint64_t P9A__SM3_CERR_HOLD0 = 0x05011575ull;