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Axone tp_chiplet_init sequence in boot
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- Initial steps of SBE
- pibmem repair (to be added later)
- Clock start sequence
- Set pcb to pcb path

Change-Id: I71b13380a6d22944625b3580583901bcf74a8279
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65273
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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@sgupta2m
Raja Das authored and sgupta2m committed Oct 1, 2018
1 parent 5833ebe commit 0297fe8
Showing 1 changed file with 90 additions and 29 deletions.
119 changes: 90 additions & 29 deletions src/boot/pibmem_repair/scom_repair_axone/pibmem_repair.S
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Original file line number Diff line number Diff line change
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/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
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.set d0 , 0
.text
.section .loader_text, "ax", @progbits


_pibmemRepair:

_liw %r3, SBE_FIXED_SECTION # Fixed Section Location
_liw %r9, SBE_SEEPROM_BASE_ORIGIN
lwz r8, 0(r3) # offset of Fixed section
adde r8, r8, r9 # add base address to offset to get absolute address
lis r5, 0x8
ori r5, r5 , 0x800B #point to repair reg 0 addr
lis r0, 0x4000 # load repair #0 with 0x4000_0000 --> enable fence and repr_mux_sel is disabled
stvd d0, 0(r5)
lvd d0, 0(r8) # r8 was pointing to attributes
stvd d0, 1(r5) # store repair reg 1
lvd d0, 8(r8) # r8 was pointing to attributes
stvd d0, 2(r5) # store repair reg 2
lvd d0, 16(r8) # r8 was pointing to attributes
stvd d0, 3(r5) # store repair reg 3
lis r0, 0x8000 # load repair #0 with 0x8000_0000 --> disable fence and repr_mux_sel is enabled
stvd d0 , 0(r5)

###################################################################
########### Update DBG_LCL_REG to enable trace ####################
###################################################################

lis r5, 0xc000 # local_reg_addr (R5 = C0000120)
ori r5, r5, 0x0120
andi. r0, r0, 0x0
andi. r1, r1, 0x0
oris r0, r0, 0x8A00 # set the bit 0 to enable the debug blot-on
stvd d0, 0(r5) # DBG_LCL_REG

blr # back to l1_loader
### switch pcb mux settings to intermediate state
_liw %r3, 0x50010
lvd d0, 0(r3) # read data from 0x50010
_liw %r5, 0x00003000 # Set Bit 18 & 19 Mask
or r0, r0, r5 # Read modify, set bit 18/19
_liw %r5, 0xFFFF7FFF # Reset Bit 16 Mask
and r0, r0, r5 # Read Modify, reset bit 16
stvd d0, 0(r3) # putscom 50010 Set bit 18/19 and
# reset bit 16

### switch pcb mux settings to pib2pcb path
lvd d0, 0(r3) # read data from 0x50010
_liw %r5, 0x00002000 # Set Bit 18 Mask
or r0, r0, r5 # Read modify, set bit 18
_liw %r5, 0xFFFF6FFF # Reset Bit 16 and 19 Mask
and r0, r0, r5 # Read Modify, reset bit 16 and 19
stvd d0, 0(r3) # putscom 50010 Set bit 18 and
# reset bit 16/19

### release pcb reset
lvd d0, 0(r3) # read data from 0x50010
_liw %r5, 0xFFFFFFFD # Reset Bit 30 Mask
and r0, r0, r5 # Read Modify, reset bit 30
stvd d0, 0(r3) # putscom 50010 reset bit 30

### Pibmem repair code here
###########################

###########################

### Set chiplet enable
_liw %r3, 0x5001a # Register 5001A
lvd d0, 0(r3) # read data from 0x5001A
_liw %r5, 0x80000000 # Set Bit 0 Mask
or r0, r0, r5 # Read modify, set bit 0
stvd d0, 0(r3) # putscom 5001A Set bit 0

### Drop TP Chiplet Fence Enable
lvd d0, 0(r3) # read data from 0x5001A
_liw %r5, 0xFFFFDFFF # Reset Bit 18 Mask
and r0, r0, r5 # Read Modify, reset bit 18
stvd d0, 0(r3) # putscom 5001A reset bit 18

### Drop clock region fences for PIB, NET
_liw %r3, 0x01000021 # Address wo_clear for 01000001
_liw %r4, 0x06000000 # Bit 5 and 6 Set for wo_clear
_liw %r5, 0x00000000 # clears bits in r5
stvd d4, 0(r3) # putscom 0x01000021 Set bit 5&6

### Start pervasive bus clocks (PIB & NET)
_liw %r3, 0x01030006 # Address
_liw %r0, 0x46000000 # load data higher 4 bytes
_liw %r1, 0x0000E000 # load data lower 4 bytes
stvd d0, 0(r3) # putscom 01030006 460000000000E000

### Set PCB Reset
_liw %r3, 0x50010
lvd d0, 0(r3) # read data from 0x50010
_liw %r5, 0x2 # Set Bit 30 Mask
or r0, r0, r5 # Read modify, set bit 30
stvd d0, 0(r3) # putscom 50010 Set bit 30

### switch pcb mux settings to intermediate state
lvd d0, 0(r3) # read data from 0x50010
_liw %r5, 0x00003000 # Set Bit 18 & 19 Mask
or r0, r0, r5 # Read modify, set bit 18/19
_liw %r5, 0xFFFF7FFF # Reset Bit 16 Mask
and r0, r0, r5 # Read Modify, reset bit 16
stvd d0, 0(r3) # putscom 50010 Set bit 18/19 and
# reset bit 16

### switch pcb mux settings to pcb2pcb path
lvd d0, 0(r3) # read data from 0x50010
_liw %r5, 0x00001000 # Set Bit 19 Mask
or r0, r0, r5 # Read modify, set bit 19
_liw %r5, 0xFFFF5FFF # Reset Bit 16 & 18 Mask
and r0, r0, r5 # Read Modify, reset bit 16 & 18
stvd d0, 0(r3) # putscom 50010 reset bit 16,18
# and set bit 19

### Release PCB Reset
lvd d0, 0(r3) # read data from 0x50010
_liw %r5, 0xFFFFFFFD # Reset Bit 30 Mask
and r0, r0, r5 # Read Modify, reset bit 30
stvd d0, 0(r3) # putscom 50010 reset bit 30

blr # back to l1_loader

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