Only attempt to quiesce PHB target if it actually exists

There was recent changes to remove one of the PHB targets for PEC1
This was causing MPIPL to break because there is some pretty rigid
code responsible for quiescing the PHBs during MPIPL. There are
future changes coming that allow the SBE to be aware of PHB states
that will allow for this code to be rewritten so we can avoid having
to look at these CPLT_CONF_IOVALID bits all together.

Change-Id: Ib8b8ac3377d8f185451716b6b7f1753de8c29268
CQ: SW374182
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41889
Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41902
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C

@@ -249,9 +249,23 @@ extern "C" {
             }
             else if (l_pci_id == 0xe)
             {
-                num_phbs = 2;
-                phb_absolute_address_array[0] = PHB_1_PHB4_SCOM_HVIAR;
-                phb_absolute_address_array[1] = PHB_2_PHB4_SCOM_HVIAR;
+                //Need to make sure that tc_pci1_iovalid(2) is 0b1 to access PHB2
+                fapi2::buffer<uint64_t> l_perv_pci1_cplt_conf1_data(0);
+                fapi2::getScom(i_target, PEC_1_CPLT_CONF1, l_perv_pci1_cplt_conf1_data);
+
+                if(l_perv_pci1_cplt_conf1_data.getBit<PEC_CPLT_CONF1_IOVALID_5D>())
+                {
+                    // PHB 2 is enabled
+                    num_phbs = 2;
+                    phb_absolute_address_array[0] = PHB_1_PHB4_SCOM_HVIAR;
+                    phb_absolute_address_array[1] = PHB_2_PHB4_SCOM_HVIAR;
+                }
+                else
+                {
+                    // PHB2 is disabled
+                    num_phbs = 1;
+                    phb_absolute_address_array[0] = PHB_1_PHB4_SCOM_HVIAR;
+                }
             }
             else if (l_pci_id == 0xf)
             {