Enable read VREF calibration

  Slow the vref cal to as slow as possible
  Update unit tests, add changes to master for f/w

Depends-On: Iab8e21a934368fcf201f0e7b91aa8b859b3b0e47
Change-Id: I1da1e0de254f2b2671c9c7d555620ef3cd3cb6a4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31556
Dev-Ready: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69790
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml

@@ -1927,7 +1927,7 @@
         <id>ATTR_MSS_CAL_STEP_ENABLE</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            A bit vector denoting valid cal steps to run (0 is left most bit)
+            A bit map of vector denoting valid cal steps to run (0 is left most bit)
             [0] EXT_ZQCAL
             [1] WR_LEVEL
             [2] DQS_ALIGN