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Revert "Adding p9a support."
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This reverts commit 41352b2d444e98639eedc06b1eb0d8da89d4adb3.

Change-Id: Ic3f2099eff3f5c942ef8fb6916e8ee78ca1a9e82
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50703
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50722
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Jennifer A. Stofer authored and Stephen M. Cprek committed Dec 14, 2017
1 parent f14d2ae commit 29a1f89
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Showing 5 changed files with 34 additions and 180 deletions.
4 changes: 1 addition & 3 deletions src/import/chips/common/utils/imageProcs/common_ringId.H
View file
Expand Up @@ -134,14 +134,13 @@ enum TorMagicNum


//
// Chip types and List to represent p9n, p9c, p9a, cen (centaur)
// Chip types and List to represent p9n, p9c, cen (centaur)
// NB! There's a matching CHIP_TYPE_LIST definition in common_ringId.C
//
enum ChipType
{
CT_P9N, // ==P9 for now
CT_P9C, // ==P9 for now
CT_P9A,
CT_CEN,
NUM_CHIP_TYPES
};
Expand All @@ -156,7 +155,6 @@ static const ChipTypeList_t CHIP_TYPE_LIST[] =
{
{"p9n", CT_P9N},
{"p9c", CT_P9C},
{"p9a", CT_P9A},
{"cen", CT_CEN},
};

Expand Down
10 changes: 4 additions & 6 deletions src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C
View file
Expand Up @@ -71,7 +71,7 @@ fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
fapi2::buffer<uint64_t> l_scom_buffer;
{
if (((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6)
&& (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
FAPI_TRY(fapi2::getScom( TGT0, 0x1001180full, l_scom_buffer ));

Expand Down Expand Up @@ -139,8 +139,7 @@ fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
if ((l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_GROUP))
{
Expand All @@ -155,15 +154,14 @@ fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_CERRS_LRU_DECR_EN_CFG_ON = 0x1;
l_scom_buffer.insert<30, 1, 63, uint64_t>(l_EXP_L3_L3_MISC_L3CERRS_L3_CERRS_LRU_DECR_EN_CFG_ON );
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6)
&& (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_OFF))
{
Expand Down
18 changes: 6 additions & 12 deletions src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
View file
Expand Up @@ -117,8 +117,7 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
l_scom_buffer.insert<8, 3, 61, uint64_t>(literal_0x3 );
}
Expand All @@ -127,8 +126,7 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
}
{
if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
FAPI_TRY(fapi2::getScom( TGT0, 0x5012c1dull, l_scom_buffer ));

Expand Down Expand Up @@ -197,8 +195,7 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
constexpr auto l_NMMU_MM_CFG_NMMU_CTL_TW_LCO_RDX_EN_ON = 0x1;
l_scom_buffer.insert<44, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TW_LCO_RDX_EN_ON );
Expand All @@ -220,8 +217,7 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
}
{
if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
FAPI_TRY(fapi2::getScom( TGT0, 0x5012c54ull, l_scom_buffer ));

Expand All @@ -237,8 +233,7 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
l_scom_buffer.insert<53, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TLB_ISS543B_FIX_EN_ON );

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
constexpr auto l_NMMU_MM_MPSS_MODE_MPSS_ENA_PREF_PGSZ_ENA_G_64KB_H_64KB = 0x155;
l_scom_buffer.insert<19, 1, 54, uint64_t>(l_NMMU_MM_MPSS_MODE_MPSS_ENA_PREF_PGSZ_ENA_G_64KB_H_64KB );
Expand All @@ -258,8 +253,7 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
constexpr auto l_NMMU_MM_CFG_TWSM_SPLIT_MODE_TWSM_SPLIT_08_TLB_04_SLB = 0x0;
l_scom_buffer.insert<57, 1, 63, uint64_t>(l_NMMU_MM_CFG_TWSM_SPLIT_MODE_TWSM_SPLIT_08_TLB_04_SLB );
Expand Down
18 changes: 6 additions & 12 deletions src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C
View file
Expand Up @@ -61,8 +61,7 @@ fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
l_scom_buffer.insert<9, 1, 63, uint64_t>(l_EXP_NC_NCMISC_NCSCOMS_SYSMAP_SM_NOT_LG_SEL_OFF );

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
if ((l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_GROUP))
{
Expand All @@ -84,30 +83,26 @@ fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
constexpr auto l_EXP_NC_NCMISC_NCSCOMS_TLBIE_PACING_CNT_EN_ON = 0x1;
l_scom_buffer.insert<10, 1, 63, uint64_t>(l_EXP_NC_NCMISC_NCSCOMS_TLBIE_PACING_CNT_EN_ON );
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
l_scom_buffer.insert<19, 8, 56, uint64_t>(literal_0x3 );
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
l_scom_buffer.insert<11, 8, 56, uint64_t>(literal_0x4 );
}

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
l_scom_buffer.insert<27, 8, 56, uint64_t>(literal_0x4 );
}
Expand All @@ -129,8 +124,7 @@ fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
FAPI_TRY(fapi2::getScom( TGT0, 0x1001100cull, l_scom_buffer ));

if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11))
|| ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
&& (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
{
constexpr auto l_EXP_NC_NCMISC_NCSCOMS_TLBIE_PACING_MST_DLY_EN_ON = 0x1;
l_scom_buffer.insert<16, 1, 63, uint64_t>(l_EXP_NC_NCMISC_NCSCOMS_TLBIE_PACING_MST_DLY_EN_ON );
Expand Down
164 changes: 17 additions & 147 deletions src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
View file
Expand Up @@ -30,153 +30,6 @@

<attributes>

<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_SEPARATE_CORE_DBG_CNTL</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
The chip had a consolodated npu_top.
True for Nimbus and Cumulus, not Axone
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_AXONE</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_ONE_NPU_TOP</id>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
The chip had a consolodated npu_top.
True for Nimbus and Cumulus, not Axone
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_ALINK</id>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
Returns true if the chip has an A-Link
(Nimbus and Cumulus, not Axone)
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_NOT_DD1_FBC_AND_ALINK</id>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
DD1 FBC setting differs from DD2, ex. lo_limit adjustment.
Axone does not have A-link support
True if Nimbus dd2 or greater or cumulus
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x20</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>

<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_NO_NPU2_FIR</id>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
Nimbus DD1 only: NPU2 FIR not present
Axone, does not have a single npu_top. Instead
it has npu_top0..2
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x20</value>
<test>LESS_THAN</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_AXONE</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_CORE_LOCAL_TRACE2</id>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
<description>
Does the core has TRACE2 with LOCAL dial names
(Nimbus dd2.X and Cumulus, Not Axone)
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x20</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
<chip>
<name>ENUM_ATTR_NAME_CUMULUS</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>

<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_HW416934_HW419818</id>
Expand Down Expand Up @@ -5470,6 +5323,23 @@
</chipEcFeature>
</attribute>

<attribute>
<id>ATTR_CHIP_EC_FEATURE_NO_NPU2_FIR</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
Nimbus DD1 only: NPU2 FIR not present
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_NIMBUS</name>
<ec>
<value>0x20</value>
<test>LESS_THAN</test>
</ec>
</chip>
</chipEcFeature>
</attribute>

<!-- ******************************************************************** -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_HW399466</id>
Expand Down

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