Clear disable_ppm_writes bit on CPPM register prior to setting PFDLY

We were hitting problems in the MPIPL path where this bit was set
causing scom writes to the PFDLY register to fail

CQ: SW398564
Change-Id: Idd13cb3b8fe2ba90fceb37c330f06adcf11a44ad
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44759
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44774
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C

@@ -378,6 +378,13 @@ fapi2::ReturnCode p9_sbe_select_ex(
         FAPI_DBG("Scoreboard values for OCC: Core 0x%016llX  EX 0x%016llX",
                  l_core_config, l_quad_config);
 
+        // Prior to writing to PFET_DELAY register, ensure that the PPM write disable
+        // bit on the Core Power Management Mode Register is cleared
+        FAPI_DBG("Clearing WRITE_DISABLE bit in core %d", l_core_num);
+        l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_DISABLE>();
+
+        FAPI_TRY(fapi2::putScom(core, C_CPPM_CPMMR_CLEAR , l_data64));
+
         // Write the default PFET Controller Delay values for the Core
         // as it will be used for istep 4
         FAPI_DBG("Setting PFET Delays in core %d", l_core_num);

src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H

@@ -46,6 +46,7 @@
 #include <p9_quad_scom_addresses.H>
 #include <p9_perv_scom_addresses.H>
 #include <p9n2_perv_scom_addresses_fld.H>
+#include <p9_quad_scom_addresses_fld.H>
 
 namespace p9selectex
 {