Add in L1 draminit_training_adv files

Change-Id: I1a79898572e675242f0c572bd708bbc05b63039d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44604
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69805
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml

@@ -1967,6 +1967,25 @@
         <mssAccessorName>cal_step_enable</mssAccessorName>
     </attribute>
 
+    <attribute>
+        <id>ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Special training pattern used for draminit_training_advance. Used for read centering
+            There can be two patterns used here.
+            The first 0-15 bits are for PATTERN1,
+            bits 16-32 are for PATTERN2.
+            If this attribute is set to 0, using the default values of:
+            0x952D for PATTERN1
+            0x594A for PATTERN2
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint32</valueType>
+        <writeable/>
+        <array>2</array>
+        <mssAccessorName>custom_training_adv_pattern</mssAccessorName>
+    </attribute>
+
     <attribute>
         <id>ATTR_MSS_VREF_CAL_ENABLE</id>
         <targetType>TARGET_TYPE_MCS</targetType>