p9_sbe_lpc_init: Improve reset

The sequence to switch the LPC HC clock onto the nest clock temporarily
was incorrect as it used the TP CPLT_CTRL0 register inasted of N3, so it
never really switched the clocks during reset. Also, for good measure,
keep the clock switched to the nest clock while we're resetting the LPC
bus.

(Bonus change: Decrease the sim delay cycles waiting for a command to
complete.)

Change-Id: I5e77fa056204639a96aad9c1eec4b7bc76d8e54b
CQ: SW439536
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63279
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63286
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/hwp/perv/p9_lpc_utils.H

@@ -30,7 +30,7 @@
 #define P9_LPC_UTILS_H_
 
 const uint32_t LPC_CMD_TIMEOUT_DELAY_NS = 1000000;
-const uint32_t LPC_CMD_TIMEOUT_DELAY_CYCLE = 80000000;
+const uint32_t LPC_CMD_TIMEOUT_DELAY_CYCLE = 1000000;
 const uint32_t LPC_CMD_TIMEOUT_COUNT = 20;
 
 static fapi2::ReturnCode lpc_rw(

src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C

@@ -47,6 +47,16 @@
 const bool LPC_UTILS_TIMEOUT_FFDC = true;
 #include "p9_lpc_utils.H"
 
+static fapi2::ReturnCode switch_lpc_clock_mux(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip,
+    bool use_nest_clock)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    l_data64.flush<0>();
+    l_data64.setBit<1>();
+    return fapi2::putScom(i_target_chip, use_nest_clock ? PERV_N3_CPLT_CTRL0_OR : PERV_N3_CPLT_CTRL0_CLEAR, l_data64);
+}
+
 static fapi2::ReturnCode reset_lpc_master(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
@@ -57,18 +67,6 @@ static fapi2::ReturnCode reset_lpc_master(
     l_data64.flush<0>().setBit<CPLT_CONF1_TC_LP_RESET>();
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_OR, l_data64));
 
-    // set LPC clock mux select to internal clock
-    //Setting CPLT_CTRL0 register value
-    l_data64.flush<0>();
-    l_data64.setBit<1>();  //PERV.CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL0_OR, l_data64));
-
-    // set LPC clock mux select to external clock
-    //Setting CPLT_CTRL0 register value
-    l_data64.flush<0>();
-    l_data64.setBit<1>();  //PERV.CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 0
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL0_CLEAR, l_data64));
-
     //Turn off the LPC functional reset
     l_data64.flush<0>().setBit<CPLT_CONF1_TC_LP_RESET>();
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_CLEAR, l_data64));
@@ -144,6 +142,9 @@ fapi2::ReturnCode p9_sbe_lpc_init(
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SP_MODE, i_target_chip, l_is_fsp), "Error getting ATTR_IS_SP_MODE");
 
+    /* The next two steps have to take place with the nest clock muxed into the LPC clock so all the logic sees its resets */
+    FAPI_TRY(switch_lpc_clock_mux(i_target_chip, true));
+
     //------------------------------------------------------------------------------------------
     //--- STEP 1: Functional reset of LPC Master
     //------------------------------------------------------------------------------------------
@@ -162,6 +163,9 @@ fapi2::ReturnCode p9_sbe_lpc_init(
         FAPI_TRY(reset_lpc_bus_via_gpio(i_target_chip));
     }
 
+    /* We can flip the LPC clock back to the external clock input now */
+    FAPI_TRY(switch_lpc_clock_mux(i_target_chip, false));
+
     //------------------------------------------------------------------------------------------
     //--- STEP 3: Program settings in LPC Master and FPGA
     //------------------------------------------------------------------------------------------