Add MSS customization support from CRP0 Lx MVPD

  Keyword V0 offsets are the same as V1
  Move bad-bits error processing to 1.03

Change-Id: I5c54911b1573b7609bb5a23634dddf5a01da8642
Original-Change-Id: I01e44c83f775b77e4ecc7afd7a5d92db524dfc98
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34073
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69795
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml

@@ -2166,11 +2166,12 @@
 
     <attribute>
         <id>ATTR_MSS_VREF_DAC_NIBBLE</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
-        <description>Value for VREF DAC nibbles</description>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>Value for VREF DAC nibble</description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
+        <array> 2 </array>
         <mssAccessorName>vref_dac_nibble</mssAccessorName>
     </attribute>
 
@@ -3117,4 +3118,17 @@
         <mssAccessorName>ignore_plug_rules</mssAccessorName>
     </attribute>
 
+    <attribute>
+        <id>ATTR_MSS_MVPD_FWMS</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+          Mark store records from MPVD Lx keyword
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint32</valueType>
+        <writeable/>
+        <array> 2 8 </array>
+        <mssAccessorName>mvpd_fwms</mssAccessorName>
+    </attribute>
+
 </attributes>