p9_sbe_tp_chiplet_init3: Don't meddle with osclite controls on Cumulus

During the clock_test2 substep, the procedure would unconditionally
clear use_osc_1_0 from ROOT_CTRL3, which turns the use_osc field (that
has been set up in istep 0) into an invalid value and breaks redundant
PCI clock failover.

Not removing that piece of code altogether because it does not appear
to hurt anything on Nimbus and it was explicitly requested by Uli back
in the Nimbus days, even though we don't remember his rationale.

Change-Id: Ieffe1946980a65c302f60d80f83b527e24d74b3b
CQ: SW434930
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61188
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61230
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C

@@ -311,24 +311,24 @@ static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2(
     l_data64.setBit<PERV_ROOT_CTRL6_SET_TPFSI_OSCSW1_PGOOD>();
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL6_SCOM, l_data64));
 
-    //Getting ROOT_CTRL3 register value
-    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL3_SCOM,
-                            l_read)); //l_read = PIB.ROOT_CTRL3
-
-    l_read.clearBit<17>();
-
-    FAPI_DBG("turn off use_osc_1_0");
-    //Setting ROOT_CTRL3 register value
-    //PIB.ROOT_CTRL3 = l_read
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, l_read));
-
     if (cumulus_only_ec_attr)  //Cumulus only
     {
         FAPI_DBG("Cumulus - Mask OSC err");
         FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_OSCERR_MASK, P9C_OSC_ERROR_MASK));
     }
     else
     {
+        //Getting ROOT_CTRL3 register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL3_SCOM,
+                                l_read)); //l_read = PIB.ROOT_CTRL3
+
+        l_read.clearBit<17>();
+
+        FAPI_DBG("turn off use_osc_1_0");
+        //Setting ROOT_CTRL3 register value
+        //PIB.ROOT_CTRL3 = l_read
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, l_read));
+
         FAPI_DBG("Mask OSC err");
         //Setting OSCERR_MASK register value
         //PIB.OSCERR_MASK = OSC_ERROR_MASK