Updates training advanced and adds custom WR CTR

Breaks apart and reorganizes training advanced code
Adds custom pattern WR CTR in training advanced
Updates custom WR/RD patterns for characterization data

Change-Id: I3fc6e515f0ae2f853ce53a198a82b7513da4eea5
CQ:SW411492
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50118
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69810
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml

@@ -1951,8 +1951,9 @@
           [17] WRITE_CTR
           [18] COARSE_WR
           [19] COARSE_RD
-          [20] TRAINING_ADV Only set for DD2.* machines
-          [21]:[31] Reserved for future use
+          [20] TRAINING_ADV_RD Only set for DD2.* machines
+          [21] TRAINING_ADV_WR Only set for DD2.* machines
+          [22]:[31] Reserved for future use
 
           COARSE_WR and COARSE_RD  will be consumed together to form COARSE_LVL.
 
@@ -1973,7 +1974,7 @@
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             Special training pattern used in draminit_training_advance.
-            Used for custom pattern write
+            Used for custom pattern read
             There can be two patterns used here.
             This attribute is before swizzling for endianness of the registers.
             CODE WILL SWIZZLE FOR THE SYSTEM
@@ -1997,7 +1998,7 @@
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             Special training backup pattern
-            Used for custom_pattern_write in draminit_training_advance.
+            Used for custom_pattern_read in draminit_training_advance.
             If the main patterns fail, the code will try running this pattern
             Used for read centering
             There can be two patterns used here.
@@ -2018,6 +2019,27 @@
         <mssAccessorName>custom_training_adv_backup_patterns</mssAccessorName>
     </attribute>
 
+    <attribute>
+        <id>ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Special training pattern used in draminit_training_advance.
+            Used for custom pattern write
+            Due to hardware limitations, only one 8-bit pattern can be used
+            This attribute is before swizzling for endianness of the registers.
+            CODE WILL SWIZZLE FOR THE SYSTEM
+            If this attribute is set to 0, using the default values of:
+            0x9A
+            Set to default in eff_config
+        </description>
+        <valueType>uint8</valueType>
+        <initToZero></initToZero>
+        <enum>DEFAULT = 0x69</enum>
+        <writeable/>
+        <array>2</array>
+        <mssAccessorName>custom_training_adv_wr_pattern</mssAccessorName>
+    </attribute>
+
     <attribute>
         <id>ATTR_MSS_VREF_CAL_ENABLE</id>
         <targetType>TARGET_TYPE_MCS</targetType>