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S0/S1 enabled for SBE
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RTC: 159756

Change-Id: I01532623ea575fa669be28b3c19bac9c8cd7e7b4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49474
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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@sgupta2m
Raja Das authored and sgupta2m committed Apr 9, 2018
1 parent 6d47311 commit 6efa7f0
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Showing 13 changed files with 490 additions and 129 deletions.
5 changes: 5 additions & 0 deletions src/build/img_defs.mk
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Expand Up @@ -467,6 +467,11 @@ endif
ifeq ($(img), pibmem)
GCC-DEFS += -DPIBMEM_ONLY_IMAGE
endif

ifeq ($(SBE_S0_SUPPORT), 1)
GCC-DEFS += -D_S0_=$(SBE_S0_SUPPORT)
endif

############################################################################
CFLAGS =
PPE-CFLAGS = $(CFLAGS) -c $(GCC-CFLAGS) $(PIPE-CFLAGS) $(GCC-O-LEVEL) $(INCLUDES)
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2 changes: 2 additions & 0 deletions src/build/power_defs.mk
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Expand Up @@ -34,6 +34,8 @@ FAPI_TRACE_LEVEL_DEF = 2

HOST_INTERFACE_AVAILABLE = 1

export SBE_S0_SUPPORT = 1

ISTEP2_INFRA_DIR = $(IMPORT_HWP_MK_DIR)/istep2
ISTEP3_INFRA_DIR = $(IMPORT_HWP_MK_DIR)/istep3
ISTEP4_INFRA_DIR = $(IMPORT_HWP_MK_DIR)/istep4
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1 change: 0 additions & 1 deletion src/sbefw/app/power/chipop_table.C
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,6 @@
#include "sbecmdtracearray.H"
#include "sbecmdCntrlTimer.H"
#include "sbecmdfastarray.H"

#include "core/chipop_handler.H"
#include "app/common/sbecmdgeneric.H"

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243 changes: 157 additions & 86 deletions src/sbefw/app/power/sbecmdmpipl.C
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Original file line number Diff line number Diff line change
Expand Up @@ -81,6 +81,71 @@ static const uint32_t ISTEP_MINOR_START = 1;
static const uint32_t ISTEP4_MAX_SUBSTEPS = 34;
static const uint32_t ISTEP5_MAX_SUBSTEPS = 2;

ReturnCode startMpiplIstepsExecute(void)
{
#define SBE_FUNC " startMpiplIstepsExecute "
SBE_ENTER(SBE_FUNC);
ReturnCode fapiRc = FAPI2_RC_SUCCESS;

uint32_t minor = 1;
do
{
fapiRc = sbeExecuteIstep(SBE_ISTEP_MPIPL_START, minor);
if(fapiRc != FAPI2_RC_SUCCESS)
{
SBE_ERROR(SBE_FUNC "Failed in StartMpipl Minor Isteps[%d]", minor);
break;
}
++minor;
}while(minor<=MPIPL_START_MAX_SUBSTEPS);

SBE_EXIT(SBE_FUNC);
return fapiRc;
#undef SBE_FUNC
}

static const uint8_t g_continuempipl_isteps[3][3] = {
// Major Num, Minor Start, Minor End
{SBE_ISTEP_MPIPL_CONTINUE, ISTEP_MINOR_START, MPIPL_CONTINUE_MAX_SUBSTEPS},
{SBE_ISTEP4, ISTEP_MINOR_START, ISTEP4_MAX_SUBSTEPS},
{SBE_ISTEP5, ISTEP_MINOR_START, ISTEP5_MAX_SUBSTEPS}};


ReturnCode continueMpiplIstepsExecute(const sbeRole i_sbeRole)
{
#define SBE_FUNC " continueMpiplIstepsExecute "
SBE_ENTER(SBE_FUNC);
ReturnCode fapiRc = FAPI2_RC_SUCCESS;

// Loop through isteps
for( auto istep : g_continuempipl_isteps )
{
for(uint8_t minor = istep[1]; minor <= istep[2]; minor++)
{
fapiRc = sbeExecuteIstep(istep[0], minor);
if(fapiRc != FAPI2_RC_SUCCESS)
{
SBE_ERROR(SBE_FUNC "Failed in Master ContinueMpipl Isteps "
"Major[%d] Minor[%d]", istep[0], minor);
break;
}
}
if(fapiRc != FAPI2_RC_SUCCESS)
{
break;
}
if(i_sbeRole == SBE_ROLE_SLAVE)
{
(void)SbeRegAccess::theSbeRegAccess().stateTransition(
SBE_RUNTIME_EVENT);
break;
}
}
SBE_EXIT(SBE_FUNC);
return fapiRc;
#undef SBE_FUNC
}

///////////////////////////////////////////////////////////////////////
// @brief sbeEnterMpipl Sbe enter MPIPL function
//
Expand All @@ -90,62 +155,55 @@ uint32_t sbeEnterMpipl(uint8_t *i_pArg)
{
#define SBE_FUNC " sbeEnterMpipl "
SBE_ENTER(SBE_FUNC);
uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
uint32_t l_fapiRc = FAPI2_RC_SUCCESS;
uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
ReturnCode fapiRc = FAPI2_RC_SUCCESS;
uint32_t len = 0;
sbeRespGenHdr_t l_respHdr;
l_respHdr.init();
sbeResponseFfdc_t l_ffdc;

sbeResponseFfdc_t ffdc;
sbeRespGenHdr_t respHdr;
respHdr.init();

do
{
// Dequeue the EOT entry as no more data is expected.
l_rc = sbeUpFifoDeq_mult (len, NULL);
CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(l_rc);
rc = sbeUpFifoDeq_mult (len, NULL);
CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(rc);

uint32_t l_minor = 1;
do
fapiRc = startMpiplIstepsExecute();
bool checkstop = isSystemCheckstop();
if((fapiRc != FAPI2_RC_SUCCESS) || checkstop)
{
l_fapiRc = sbeExecuteIstep(SBE_ISTEP_MPIPL_START, l_minor);
bool checkstop = isSystemCheckstop();
if((l_fapiRc != FAPI2_RC_SUCCESS) || checkstop)
SBE_ERROR(SBE_FUNC "Failed in Mpipl Start in ChipOp Mode");
if(checkstop)
{
SBE_ERROR(SBE_FUNC "Failed in Mpipl Start in ChipOp Mode "
"Minor: %d", l_minor);
if(checkstop)
{
l_respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
SBE_SEC_SYSTEM_CHECKSTOP);
}
else
{
l_respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
l_ffdc.setRc(l_fapiRc);
}
// reset attribute. We do not want to reset register, so do not
// use setMpIplMode
uint8_t isMpipl = 0;
PLAT_ATTR_INIT(ATTR_IS_MPIPL, Target<TARGET_TYPE_SYSTEM>(),
isMpipl);
break;
respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
SBE_SEC_SYSTEM_CHECKSTOP);
}
++l_minor;
}while(l_minor<=MPIPL_START_MAX_SUBSTEPS);

else
{
respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
ffdc.setRc(fapiRc);
}
// reset attribute. We do not want to reset register, so do not
// use setMpIplMode
uint8_t isMpipl = 0;
PLAT_ATTR_INIT(ATTR_IS_MPIPL, Target<TARGET_TYPE_SYSTEM>(), isMpipl);
break;
}
}while(0);

// Create the Response to caller
do
{
// If there was a FIFO error, will skip sending the response,
// instead give the control back to the command processor thread
CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(l_rc);
l_rc = sbeDsSendRespHdr( l_respHdr, &l_ffdc);
CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(rc);
rc = sbeDsSendRespHdr( respHdr, &ffdc);
}while(0);

SBE_EXIT(SBE_FUNC);
return l_rc;
return rc;
#undef SBE_FUNC
}

Expand All @@ -158,66 +216,42 @@ uint32_t sbeContinueMpipl(uint8_t *i_pArg)
{
#define SBE_FUNC " sbeContinueMpipl "
SBE_ENTER(SBE_FUNC);
uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL;
uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
ReturnCode fapiRc = FAPI2_RC_SUCCESS;
uint32_t len = 0;

ReturnCode l_fapiRc = FAPI2_RC_SUCCESS;
sbeResponseFfdc_t l_ffdc;
sbeRespGenHdr_t l_respHdr;
l_respHdr.init();
sbeResponseFfdc_t ffdc;
sbeRespGenHdr_t respHdr;
respHdr.init();

do
{
// Dequeue the EOT entry as no more data is expected.
l_rc = sbeUpFifoDeq_mult (len, NULL);
CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(l_rc);
rc = sbeUpFifoDeq_mult (len, NULL);
CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(rc);

sbeRole l_sbeRole = SbeRegAccess::theSbeRegAccess().isSbeSlave() ?
sbeRole sbeRole = SbeRegAccess::theSbeRegAccess().isSbeSlave() ?
SBE_ROLE_SLAVE : SBE_ROLE_MASTER;

// Run isteps
const uint8_t isteps[][3] = {
// Major Num, Minor Start, Minor End
{SBE_ISTEP_MPIPL_CONTINUE, ISTEP_MINOR_START, MPIPL_CONTINUE_MAX_SUBSTEPS},
{SBE_ISTEP4, ISTEP_MINOR_START, ISTEP4_MAX_SUBSTEPS},
{SBE_ISTEP5, ISTEP_MINOR_START, ISTEP5_MAX_SUBSTEPS}};
// Loop through isteps
for( auto istep : isteps)
fapiRc = continueMpiplIstepsExecute(sbeRole);
bool checkstop = isSystemCheckstop();
if((fapiRc != FAPI2_RC_SUCCESS) || checkstop)
{
// This is required here to skip the major istep 4/5 in slave
if((SBE_ROLE_SLAVE == l_sbeRole) &&
(istep[0] == 4 || istep[0] == 5))
SBE_ERROR(SBE_FUNC "Failed in Continue Mpipl in ChipOp Mode, "
"SBE Role[%d]", sbeRole);
if(checkstop)
{
(void)SbeRegAccess::theSbeRegAccess().stateTransition(
SBE_RUNTIME_EVENT);
continue;
respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
SBE_SEC_SYSTEM_CHECKSTOP);
}
for(uint8_t l_minor = istep[1]; l_minor <= istep[2]; l_minor++)
{
l_fapiRc = sbeExecuteIstep(istep[0], l_minor);
bool checkstop = isSystemCheckstop();
if((l_fapiRc != FAPI2_RC_SUCCESS) || checkstop)
{
SBE_ERROR(SBE_FUNC "Failed in Mpipl continue in ChipOp "
"Mode Major [%d] Minor [%d]", istep[0], l_minor);
if(checkstop)
{
l_respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
SBE_SEC_SYSTEM_CHECKSTOP);
}
else
{
l_respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
l_ffdc.setRc(l_fapiRc);
}
break;
}
}
if(l_ffdc.getRc() != FAPI2_RC_SUCCESS)
else
{
break;
respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE,
SBE_SEC_GENERIC_FAILURE_IN_EXECUTION);
ffdc.setRc(fapiRc);
// Async Response to be stored
}
break;
}
}while(0);

Expand All @@ -228,15 +262,52 @@ uint32_t sbeContinueMpipl(uint8_t *i_pArg)
// Create the Response to caller
// If there was a FIFO error, will skip sending the response,
// instead give the control back to the command processor thread
if(SBE_SEC_OPERATION_SUCCESSFUL == l_rc)
if(SBE_SEC_OPERATION_SUCCESSFUL == rc)
{
l_rc = sbeDsSendRespHdr( l_respHdr, &l_ffdc);
rc = sbeDsSendRespHdr( respHdr, &ffdc);
}
SBE_EXIT(SBE_FUNC);
return l_rc;
return rc;
#undef SBE_FUNC
}

#ifdef _S0_
///////////////////////////////////////////////////////////////////////
// @brief stopClockS0 Sbe StopClock S0 interface function
//
// @return RC from the underlying FIFO utility
///////////////////////////////////////////////////////////////////////
ReturnCode stopClockS0()
{
#define SBE_FUNC "stopClockS0"
SBE_ENTER(SBE_FUNC);
uint32_t fapiRc = FAPI2_RC_SUCCESS;
p9_stopclocks_flags flags;

p9hcd::P9_HCD_CLK_CTRL_CONSTANTS clk_regions =
p9hcd::CLK_REGION_ALL_BUT_PLL_REFR;
p9hcd::P9_HCD_EX_CTRL_CONSTANTS ex_select = p9hcd::BOTH_EX;

flags.clearAll();
flags.sync_stop_quad_clks = false;
flags.stop_core_clks = true;
flags.stop_cache_clks = true;

SBE_EXEC_HWP(fapiRc, p9_stopclocks_hwp,
plat_getChipTarget(),
flags,
clk_regions,
ex_select);
if(fapiRc != FAPI2_RC_SUCCESS)
{
SBE_ERROR(SBE_FUNC "Failed in StopClock S0S1 Interface");
}

SBE_EXIT(SBE_FUNC);
return fapiRc;
#undef SBE_FUNC
}
#endif
///////////////////////////////////////////////////////////////////////
/* @brief Deduce the type of stop clock procedure to call based on
* target and chiplet id combination
Expand Down
27 changes: 27 additions & 0 deletions src/sbefw/app/power/sbecmdmpipl.H
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
Expand All @@ -32,6 +33,7 @@
#define __SBEFW_SBECMDMPIPL_H

#include <stdint.h>
#include "sbestates.H"

/**
* @brief Handles Sbe Enter Mpipl chip-op (0xA901)
Expand Down Expand Up @@ -60,4 +62,29 @@ uint32_t sbeContinueMpipl(uint8_t *i_pArg);
*/
uint32_t sbeStopClocks(uint8_t *i_pArg);

/**
* @brief Handles Sbe Start MPIPL iSteps
*
* @return Rc from the FIFO access utility
*/
fapi2::ReturnCode startMpiplIstepsExecute(void);

/**
* @brief Handles Sbe Continue MPIPL iSteps based on Master/Slave SBE
*
* @param[in] i_sbeRole Master/Slave SBE
*
* @return Rc from the FIFO access utility
*/
fapi2::ReturnCode continueMpiplIstepsExecute(const sbeRole i_sbeRole);

#ifdef _S0_
/**
* @brief Handles Sbe Stop Clock (Core/Cache) procedure in S0 context
*
* @return Rc from the FIFO access utility
*/
fapi2::ReturnCode stopClockS0();
#endif

#endif /* __SBEFW_SBECMDMPIPL_H */

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