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CME Code Size Reduction ATTEMPT#3
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  -- some IOTA kernel cleanup
  -- also add checking for IOTA execution stack overflow
  -- re-coded to eliminate some math library macro usage
  -- added native 16-bit multiply
  -- re-coded to remove redundancy from external interrupt handler
  -- removed dec handler (optional define) and other minor cleanup
  -- fixed Interrupt initialization code in std_init (all PPE images)
  -- always inline pstate_db0_clip_bcast & update_vdm_jump_values_in_dpll
  -- optimized pls calculation code
  -- optimized pstate init, db1 handler, core good handling
  -- optimized pmcr requests and pmsr updates (always write for both cores)

Key_Cronus_Test=PM_REGRESS

Change-Id: If48fec5832bd5e46cb89f0d6a97d90a488e8ff7b
CQ: SW415503
RTC: 178789
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53381
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53385
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Michael Floyd authored and sgupta2m committed Feb 7, 2018
1 parent 513d716 commit 74c0e53
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Showing 4 changed files with 39 additions and 20 deletions.
5 changes: 4 additions & 1 deletion src/import/chips/p9/procedures/ppe/pk/kernel/pk.h
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/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
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#include "pk_kernel.h"
//#include "pk_io.h"

#define compile_assert(name,e) \
enum { compile_assert__##name = 1/(e) };

#ifndef __ASSEMBLER__

#define MIN(X, Y) \
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6 changes: 5 additions & 1 deletion src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -138,6 +138,10 @@ typedef union
asm volatile ("mfspr %0, %1" : "=r" (__value) : "i" (sprn) : "memory"); \
__value;})

#define mfpir() \
({uint32_t __value; \
asm volatile ("mfspr %0, 1023" : "=r" (__value) : : "memory"); \
__value;})

/// Move to SPR
///
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22 changes: 21 additions & 1 deletion src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42math.h
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016 */
/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand All @@ -25,6 +25,26 @@
#ifndef _MATH_H
#define _MATH_H

// Provide a way to use the native 16-bit multiply instruction
// Unfortunately the compiler does not know to use it
/// Signed 16 bit multiply, 32 bit product
#define muls16(x,y) \
({\
int32_t __x = (x); \
int32_t __y = (y); \
int32_t __z; \
asm volatile ("mullhw %0,%1,%2" : "=r" (__z) : "r" (__x), "r" (__y) : "cc"); \
__z;})

/// Unsigned 16 bit multiply, 32 bit product
#define mulu16(x,y) \
({\
uint32_t __x = (x); \
uint32_t __y = (y); \
uint32_t __z; \
asm volatile("mullhwu %0,%1,%2" : "=r" (__z) : "r" (__x), "r" (__y) : "cc"); \
__z;})

#ifdef __cplusplus
extern "C"
{
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26 changes: 9 additions & 17 deletions src/import/chips/p9/procedures/ppe/pk/std/std_init.c
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Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
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void
__hwmacro_setup(void)
{
//mask all interrupts
out64(STD_LCL_EIMR_OR, 0xffffffffffffffffull);

//Set all interrupts to active low, level sensitive by default
out64(STD_LCL_EIPR_CLR, 0xffffffffffffffffull);
out64(STD_LCL_EITR_CLR, 0xffffffffffffffffull);

//set up the configured type
out64(STD_LCL_EITR_OR, g_ext_irqs_type);
//mask all interrupts to prevent spurious pulse to PPE
out64(STD_LCL_EIMR, 0xffffffffffffffffull);

//set up the configured polarity
out64(STD_LCL_EIPR_OR, g_ext_irqs_polarity);
out64(STD_LCL_EIPR, g_ext_irqs_polarity);

//clear the status of all active-high interrupts (has no affect on
//level sensitive interrupts)
out64(STD_LCL_EISR_CLR, g_ext_irqs_polarity);
//set up the configured type
out64(STD_LCL_EITR, g_ext_irqs_type);

//clear the status of all active-low interrupts (has no affect on
//level sensitive interrupts)
out64(STD_LCL_EISR_OR, ~g_ext_irqs_polarity);
//clear the status of all edge interrupts
out64(STD_LCL_EISR_CLR, g_ext_irqs_type);

//unmask the interrupts that are to be enabled by default
out64(STD_LCL_EIMR_CLR, g_ext_irqs_enable);

//wait for the last operation to complete
sync();

}

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