PM: Prevent Core-L2 Quiesce from removing PM_EXIT upon SPWU

Key_Cronus_Test=PM_REGRESS

Change-Id: I34f08519d2c86fec2f0ee0feb96a62bd826e31fa
CQ: SW440301
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63774
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63796
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -181,6 +181,16 @@ p9_hcd_core_stopclocks(
             }
 
 #endif
+
+            //if a core is only in special wakeup and asserting pm_exit,
+            //then setting 6,7 of SICR will cause pm_exit to drop and
+            //the core will re-enter a power saving state
+            FAPI_DBG("Prevent Core-L2 Quiesce from removing PM_EXIT CME_SCOM_LMCR[22]");
+            FAPI_TRY(putScom(l_quad,
+                             (l_attr_chip_unit_pos < 2) ?
+                             EX_0_CME_SCOM_LMCR_OR : EX_1_CME_SCOM_LMCR_OR,
+                             (BIT64(22))));
+
             FAPI_DBG("Assert Core-L2/CC Quiesces via CME_SCOM_SICR[6,8]/[7,9]");
             FAPI_TRY(putScom(l_quad,
                              (l_attr_chip_unit_pos < 2) ?