add SS PLL settings to support 94 MHz PCI operation

  support PCIE on DD1.x by lowering input refclock

Change-Id: If50bd3441437f6f534e95c981e337dd9f3ef1168
Original-Change-Id: Ic69f0b4cdcba9d667d08aa37aced6dbc4c156c98
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34389
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -426,6 +426,24 @@
       </chip>
     </chipEcFeature>
   </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      DD1 only: leverage SS PLL to provide reduced frequency reference clock
+                (94 MHz, instead of nominal 100 MHz) for PCI PLL
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
 
   <!-- ******************************************************************** -->
   <!-- Memory Section                                                       -->