enforce strict 512 GB per socket limit on Witherspoon memory map

  SW415901 exposed a problem with the current implementation of extended
  addressing for Witherspoon Coral systems.  With fully configured
  memory present in the system (8x64GB=512GB per socket), GARDing a DIMM
  will currently result in:
  - group of 6 fullying occupying 0-512GB address space
  - group of 1 mapped at 8TB region (2nd extended addressing region)
  The single group mapping has RA bit 20 active, which is problematic
  for the NVIDIA device driver.

  p9_fbc_utils.H
  p9.trace.scan.initfile
    for HW423589 option 2, enable chip address extension for chip ID LSB
    RA bit 21 only.  This creates only one 4TB extended addressing
    region per socket.

    indirectly, this limits DIMMs to map into the 512 GB region with RA
    bit 21=0 and should cause an IPL failure if more than 512 GB is
    plugged or the memory grouping algorithm attempts to spill beyond
    512 GB on a given chip

  p9_mss_eff_grouping.C
    prohibit formation of group sizes 6 and 3 when HW423589 option2 WA
    is active

Change-Id: I997c080a2821cf3c556a4f8b35d5e0fdb34da500
CQ: SW415901
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53406
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53411
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -70,9 +70,9 @@ const uint64_t P9_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL;
 const uint64_t FABRIC_CACHELINE_SIZE = 0x80;
 
 // chip address extension mask, for HW423589_OPTION2
-// repurposes chip ID(0:2) as address bits
+// repurposes chip ID(2) as address bits
 const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2 = 0x0;
-const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x7;
+const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x1;
 
 const uint64_t MAX_INTERLEAVE_GROUP_SIZE                  = 0x40000000000ULL; // 4_TB
 const uint64_t MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 = 0x8000000000ULL;  // 512_GB