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Implement PBA Cache-Inhibited 8B Rd/Wr Access
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The PBA supports 8B cache-inhibited rd/wr operations via the OCB
indirect-OCI access path.

Also implemented necessary changes in the wrapper to support the PBA
cache-inhibited operations.
Turns out that the ADU cache-inhibited ops are broken in the wrapper
so I undocumented them in the wrapper's usage/help string.

Change-Id: Ic6f3d358a548a1750a779a7f17b223a275983419
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71166
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Kahn C. Evans <kahnevan@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71180
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Christopher M Riedl authored and sgupta2m committed Feb 13, 2019
1 parent 934ccd8 commit a3b2377
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Showing 4 changed files with 68 additions and 31 deletions.
9 changes: 6 additions & 3 deletions src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -68,14 +68,17 @@ extern "C" {
//if read
if (i_rnw)
{
FAPI_TRY(p9_pba_coherent_pba_read(i_target, i_address, io_data),
FAPI_TRY(p9_pba_coherent_pba_read(i_target, i_address,
l_myPbaFlag.getOperationType(),
io_data),
"p9_pba_coherent_pba_read() returns error l_rc 0x%.8X",
(uint64_t)fapi2::current_err);
}
//else if write
else
{
FAPI_TRY(p9_pba_coherent_pba_write(i_target, i_address, io_data),
FAPI_TRY(p9_pba_coherent_pba_write(i_target, i_address, io_data,
l_myPbaFlag.getOperationType()),
"p9_pba_coherent_pba_write() returns error l_rc 0x%.8X",
(uint64_t)fapi2::current_err);

Expand Down
75 changes: 52 additions & 23 deletions src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -51,7 +51,6 @@ extern "C"
//---------------------------------------------------------------------------------
// Constant definitions
//---------------------------------------------------------------------------------

//PBA Delay Constants
const uint32_t PBA_SLVRST_DELAY_HW_NS = 1000;
const uint32_t PBA_SLVRST_DELAY_SIM_CYCLES = 200;
Expand Down Expand Up @@ -88,22 +87,42 @@ extern "C"
const uint32_t OCB3_ADDRESS_REG_ADDR_SHIFT = 32;

const uint32_t FSI2PIB_RESET_PIB_RESET_BIT = 0;

//PBA CI ttype limited to 8B transfers via OCB indirect-access (others don't go through)
const uint64_t PBA_CI_TTYPE_ADDR_MASK = 0x7ul;
//---------------------------------------------------------------------------------
// Function definitions
//---------------------------------------------------------------------------------

fapi2::ReturnCode p9_pba_coherent_utils_check_args(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const uint64_t i_address)
const uint64_t i_address, const uint32_t i_flags)
{
p9_PBA_oper_flag l_myPbaFlag;
p9_PBA_oper_flag::OperationType_t l_operType;

FAPI_DBG("Start");

//Check the address alignment
FAPI_ASSERT(!(i_address & P9_FBC_UTILS_CACHELINE_MASK),
fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
i_address),
"Address is not cacheline aligned");
// Process input flag
l_myPbaFlag.getFlag(i_flags);
l_operType = l_myPbaFlag.getOperationType();

if (l_operType == p9_PBA_oper_flag::CI)
{
//Check the address alignment
FAPI_ASSERT(!(i_address & PBA_CI_TTYPE_ADDR_MASK),
fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
i_address),
"Address is not 8B aligned for cache-inhibited access");
}
else
{
//Check the address alignment
FAPI_ASSERT(!(i_address & P9_FBC_UTILS_CACHELINE_MASK),
fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
i_address),
"Address is not cacheline aligned");
}

//Make sure the address is within the PBA bounds
FAPI_ASSERT(i_address <= P9_FBC_UTILS_FBC_MAX_ADDRESS,
Expand Down Expand Up @@ -230,8 +249,16 @@ extern "C"
//set the write ttype bits 8:10 to whatever is in the flags
pba_slave_ctl_data.insertFromRight < PU_PBASLVCTL3_WRITE_TTYPE, PU_PBASLVCTL3_WRITE_TTYPE_LEN > (l_operType);

//it's not cache-inhibited so set bit 15 to cl_rd_nc (0)
pba_slave_ctl_data.clearBit<PU_PBASLVCTL3_READ_TTYPE>();
// PBA read_ttype: 0=CL_RD_NC, 1=CI_PR_RD
if (l_operType == p9_PBA_oper_flag::CI && i_rnw)
{
pba_slave_ctl_data.setBit<PU_PBASLVCTL3_READ_TTYPE>();
}
else
{
pba_slave_ctl_data.clearBit<PU_PBASLVCTL3_READ_TTYPE>();
}

//set bits 16:17 to No prefetch 01 TODO May need to change this later if we want to use prefetch
pba_slave_ctl_data.insertFromRight < PU_PBASLVCTL3_READ_PREFETCH_CTL, PU_PBASLVCTL3_READ_PREFETCH_CTL_LEN > (1);
//unset bit 18 - no auto-invalidate
Expand Down Expand Up @@ -277,18 +304,6 @@ extern "C"

FAPI_DBG("Start");

//Validate the input parameters
//Check the address alignment
FAPI_ASSERT(!(i_baseAddress & P9_FBC_UTILS_CACHELINE_MASK),
fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
i_baseAddress),
"Base Address is not cacheline aligned");
//Make sure the address is within the PBA bounds
FAPI_ASSERT(i_baseAddress <= P9_FBC_UTILS_FBC_MAX_ADDRESS,
fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
i_baseAddress),
"Base Address exceeds supported fabric real address range");

//set command scope to local node scope
pba_bar_data.insertFromRight < PU_PBABAR0_CMD_SCOPE, PU_PBABAR0_CMD_SCOPE_LEN >
(PBA_BAR_SCOPE_LOCAL_NODE);
Expand All @@ -310,7 +325,8 @@ extern "C"
fapi2::ReturnCode p9_pba_coherent_pba_write(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const uint64_t i_address,
const uint8_t i_write_data[])
const uint8_t i_write_data[],
const p9_PBA_oper_flag::OperationType_t i_ttype)
{
fapi2::ReturnCode rc;
uint64_t write_data = 0x0ull;
Expand All @@ -335,6 +351,12 @@ extern "C"
rc = p9_pba_coherent_error_handling(i_target, rc);
break;
}

// PBA cache-inhibited operations are limited to 8B
if (i_ttype == p9_PBA_oper_flag::CI)
{
break;
}
}

FAPI_DBG("End");
Expand All @@ -344,6 +366,7 @@ extern "C"
fapi2::ReturnCode p9_pba_coherent_pba_read(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const uint64_t i_address,
const p9_PBA_oper_flag::OperationType_t i_ttype,
uint8_t o_read_data[])
{
fapi2::ReturnCode rc;
Expand All @@ -367,6 +390,12 @@ extern "C"
{
o_read_data[(i * 8) + j] = (data >> (56 - (j * 8))) & 0xFFull;;
}

// PBA cache-inhibited operations are limited to 8B
if (i_ttype == p9_PBA_oper_flag::CI)
{
break;
}
}

FAPI_DBG("End");
Expand Down
11 changes: 8 additions & 3 deletions src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -221,20 +221,24 @@ extern "C"
/// @param[in] i_target => P9 chip target
/// @param[in] i_address => address for this write
/// @param[in] i_write_data => the data that is to be written to the PBA
/// @param[in] i_ttype => ttype to use for write access
/// @return FAPI_RC_SUCCESS if writing the PBA is a success
fapi2::ReturnCode p9_pba_coherent_pba_write(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const uint64_t i_address,
const uint8_t i_write_data[]);
const uint8_t i_write_data[],
const p9_PBA_oper_flag::OperationType_t i_ttype);

/// @brief does the read for the PBA
/// @param[in] i_target => P9 chip target
/// @param[in] i_address => address for this write
/// @param[in] i_ttype => ttype to use for read access
/// @param[out] o_read_data => the data that is read from the PBA
/// @return FAPI_RC_SUCCESS if reading the PBA is a success
fapi2::ReturnCode p9_pba_coherent_pba_read(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const uint64_t i_address,
const p9_PBA_oper_flag::OperationType_t i_ttype,
uint8_t o_read_data[]);

/// @brief calculates the number of 128 byte granules that can be read/written before setup needs to be run again
Expand All @@ -257,10 +261,11 @@ extern "C"
/// @brief check that the address is cacheline aligned and within the fabric real address range
/// @param[in] i_target => P9 chip target
/// @param[in] i_address => starting address for PBA operation
/// @param[in] i_flags => flags that contain information that the PBA needs to know to set up registers
/// @return FAPI_RC_SUCCESS if arguments are valid
fapi2::ReturnCode p9_pba_coherent_utils_check_args(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const uint64_t i_address);
const uint64_t i_address, const uint32_t i_flags);

/// @brief this does any cleanup for the PBA after all reads/writes have been done
/// @param[in] i_target => P9 chip target
Expand Down
4 changes: 2 additions & 2 deletions src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -61,7 +61,7 @@ extern "C"
FAPI_DBG("Entering ...\n");

//check arguments
FAPI_TRY(p9_pba_coherent_utils_check_args(i_target, i_address),
FAPI_TRY(p9_pba_coherent_utils_check_args(i_target, i_address, i_flags),
"Error from p9_pba_coherent_utils_check_args");

//ensure fabric is running
Expand Down

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