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Additional risk level support - (step 2) Updating the image w/RL2
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This commit changes the images' .rings section by adding the TOR
RL2 variant slot to the runtime Quad chiplets, EQ and EC.

Specifically, we have changed the definition of the ATTR_RISK_LEVEL
attribute to now have three risk levels, RL0 (prev FALSE), RL1
(prev TRUE) and RL2 (new). To accomodate RL2, a new "override"
txt file has been created, ./attribute_ovd/runtime_risk2.txt and
changes to many other files using the ATTR_RISK_LEVEL attrib have
been updated as well.

Lastly, and to allow for the inclusion of RL2 rings in the HW
image, the TOR_VERSION has been updated to version 6 which will
allow for RL2 support in the ring ID metadata files.

p9_setup_sbe_config is updated to write the RISK_LEVEL value into
scratch 3 bits 28:31, and deprecate the existing mailbox.

RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's
only function is to seed mailboxes which are empty via the
attribute state present in the SEEPROM.  Since RISK_LEVEL is zero
at image build time, and explicitly cleared as a result of every
customization, there's logically no need to process the RISK_LEVEL
here.

PPE changes to accomodate the new RISK_LEVEL mailbox
location need to be implemented in the PLAT code: src/hwpf/target.C

Key_Cronus_Test=XIP_REGRESS

HW-ImageBuild-Preqeq=52659
- 52659 must be fully merged in Cronus and HB before this commit
  (53292) can be merged. This is to avoid a Coreq situation.

CQ: SW416424
cmvc-prereq: 1046058
cmvc-prereq: 1043606
cmvc-prereq: 1045920
Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53322
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@cmolsen @sgupta2m
cmolsen authored and sgupta2m committed Feb 17, 2018
1 parent c955a5c commit b82c9d4
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Showing 4 changed files with 7 additions and 20 deletions.
4 changes: 2 additions & 2 deletions src/hwpf/plat_ring_traverse.C
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@
// SEEPROM start address
const uint32_t g_seepromAddr = SBE_SEEPROM_BASE_ORIGIN;
const uint32_t CACHE_CONTAINED_MODE = 4;
const uint32_t RISK_LEVEL_MODE = 1;
const uint32_t RISK_LEVEL_ZERO = 0;
#define CACHE_CONTAINED_MODE_OFFSET_IN_TOR 1
#define RISK_LEVEL_MODE_OFFSET_IN_TOR 2
#define OVERRIDE_VARIANT_SIZE 1
Expand Down Expand Up @@ -468,7 +468,7 @@ fapi2::ReturnCode getRS4ImageFromTor(
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> (),
l_riskLevel);

if((RISK_LEVEL_MODE == l_riskLevel) &&
if((RISK_LEVEL_ZERO != l_riskLevel) &&
*(l_ringTorAddr + l_RL_offset))
{
l_ringTorAddr += l_RL_offset;
Expand Down
4 changes: 2 additions & 2 deletions src/import/chips/common/utils/imageProcs/common_ringId.H
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Original file line number Diff line number Diff line change
Expand Up @@ -137,8 +137,8 @@ typedef uint16_t TorRingOffset_t; // Offset value to actual ring
//#define TOR_VERSION 2 // Reduced RS4 header.
//#define TOR_VERSION 3 // Added TOR magic header.
//#define TOR_VERSION 4 // TOR API code restructuring.
#define TOR_VERSION 5 // Removed TOR-level DD handling.
//#define TOR_VERSION 6 // Added additional runtime risk level (RL2)
//#define TOR_VERSION 5 // Removed TOR-level DD handling.
#define TOR_VERSION 6 // Added additional runtime risk level (RL2)

// TOR Magic values for top-level TOR ringSection and sub-ringSections
enum TorMagicNum
Expand Down
15 changes: 1 addition & 14 deletions src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -86,7 +86,6 @@ enum P9_SETUP_SBE_CONFIG_scratch4
ATTR_PLL_MUX_LENGTH = 20,
ATTR_CC_IPL_BIT = 0,
ATTR_INIT_ALL_CORES_BIT = 1,
ATTR_RISK_LEVEL_BIT = 2,
ATTR_DISABLE_HBBL_VECTORS_BIT = 3,
ATTR_MC_SYNC_MODE_BIT = 4,
ATTR_SLOW_PCI_REF_CLOCK_BIT = 5,
Expand Down Expand Up @@ -325,7 +324,6 @@ fapi2::ReturnCode p9_sbe_attr_setup(const

uint8_t l_system_ipl_phase = 0;
uint8_t l_force_all_cores = 0;
uint8_t l_risk_level = 0;
uint8_t l_disable_hbbl_vectors = 0;
uint32_t l_pll_mux = 0;
uint8_t l_mc_sync_mode = 0;
Expand Down Expand Up @@ -357,7 +355,6 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
FAPI_DBG("Reading control flag attributes");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_system_ipl_phase));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, l_force_all_cores));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, l_slow_pci_ref_clock));
Expand All @@ -382,16 +379,6 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
l_read_scratch_reg.clearBit<ATTR_INIT_ALL_CORES_BIT>();
}

// set risk level flag
if (l_risk_level == fapi2::ENUM_ATTR_RISK_LEVEL_TRUE)
{
l_read_scratch_reg.setBit<ATTR_RISK_LEVEL_BIT>();
}
else
{
l_read_scratch_reg.clearBit<ATTR_RISK_LEVEL_BIT>();
}

// set disable of HBBL exception vector flag
if (l_disable_hbbl_vectors == fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE)
{
Expand Down
4 changes: 2 additions & 2 deletions src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER sbe Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2017 -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2018 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
Expand Down Expand Up @@ -210,7 +210,7 @@
<description>HWP/Init "risk level" enabled. Used by HB to pass to HB driven
HWPs</description>
<valueType>uint8</valueType>
<enum>FALSE = 0x0,TRUE = 0x1</enum>
<enum>RL0 = 0x0,RL1 = 0x1,RL2 = 0x2</enum>
<persistRuntime/>
<platInit/>
</attribute>
Expand Down

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