adjust SRAM timings

Change-Id: Ic3e5e66c9076c021d023f1bc5d745e761a413ec6
Original-Change-Id: Iae2a281eeebe46f316dc4c7d23e869f103b88abb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36892
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -1184,10 +1184,10 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_L3_SRAM_RELAXED_SETTINGS</id>
+    <id>ATTR_CHIP_EC_FEATURE_SRAM_RELAXED_SETTINGS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Nimbus DD1 only: SRAM relaced settings 
+      Nimbus DD1 only: adjust/relax SRAM timing parameters
     </description>
     <chipEcFeature>
       <chip>
@@ -1322,23 +1322,6 @@
     </chipEcFeature>
   </attribute>
   <!-- ******************************************************************** -->
-  <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_L2_DUMMY_PULSE_POK_BITS</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      DD1 only: CAY_L2C_A102_MAC dummy pulse pok bits
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>LESS_THAN</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW374111</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>