Add explorer rc response to eff_config

Change-Id: I914585acdada326f191dbfb199dbdfac948b24b1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/91480
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Dev-Ready: ANDRE A MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/94044
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H

@@ -134,6 +134,35 @@ enum class attr_eff_engine_fields
     DISPATCHER = SUPPORTED_RCD,
 };
 
+///
+/// @brief enum list of explorer RC response msdg to set
+///
+enum class attr_rc_resp_engine_fields
+{
+    // Template recursive base case
+    ATTR_EFF_BASE_CASE = 0,
+
+    // Attrs to set
+    F0RC00 = 1,
+    F0RC01 = 2,
+    F0RC03 = 3,
+    F0RC04 = 4,
+    F0RC05 = 5,
+    F0RC0B = 6,
+    F0RC0E = 7,
+    F0RC0F = 8,
+    F0RC1X = 9,
+    F0RC7X = 10,
+    F1RC00 = 11,
+    F1RC02 = 12,
+    F1RC03 = 13,
+    F1RC04 = 14,
+    F1RC05 = 15,
+
+    // Dispatcher set to last enum value
+    DISPATCHER = F1RC05,
+};
+
 ///
 /// @brief common explorer sizes
 ///
@@ -148,6 +177,8 @@ enum sizes
     MAX_MRANK_PER_PORT = MAX_DIMM_PER_PORT * MAX_RANK_PER_DIMM,
     MAX_BYTES_PER_PORT = MAX_DQ_BITS_PER_PORT / BITS_PER_BYTE,
     MAX_NIBBLES_PER_PORT = MAX_DQ_BITS_PER_PORT / BITS_PER_NIBBLE,
+    MAX_RCW_RESP_ARRAY_SIZE = 27,
+
 };
 
 #endif
@@ -192,7 +223,24 @@ enum ffdc_codes
     SET_THERM_SENSOR_DIFF_TYPE = 0x105C,
     SET_THERM_SENSOR_DIFF_USAGE = 0x105D,
     SET_THERM_SENSOR_DIFF_I2C_ADDR = 0x105E,
-    SET_SUPPORTED_RCD = 0x105F,
+
+    READ_RC_RSP_FIELD = 0x105F,
+    SET_F0RC00 = 0x1060,
+    SET_F0RC01 = 0x1061,
+    SET_F0RC03 = 0x1062,
+    SET_F0RC04 = 0x1063,
+    SET_F0RC05 = 0x1064,
+    SET_F0RC0B = 0x1065,
+    SET_F0RC0E = 0x1066,
+    SET_F0RC0F = 0x1067,
+    SET_F0RC1X = 0x1068,
+    SET_F0RC7X = 0x1069,
+    SET_F1RC00 = 0x106A,
+    SET_F1RC02 = 0x106B,
+    SET_F1RC03 = 0x106C,
+    SET_F1RC04 = 0x106D,
+    SET_F1RC05 = 0x106E,
+    SET_SUPPORTED_RCD = 0x106F,
 };
 
 ///
@@ -367,7 +415,7 @@ enum addrSide
     RHS = 0x01
 };
 
-}// i2c
+} // namespace i2c
 
 #ifndef __PPE__
 namespace omi
@@ -432,10 +480,10 @@ enum response_arg
     ERROR_CODE = 1,
 };
 
-}// omi
+} // namespace omi
 #endif
 
-}// exp
-}// mss
+} // namespace exp
+} // namespace mss
 
 #endif