Expanding MCU tag fifo settings to be freq dependent.

Change-Id: I0b4b7b61a7fa4920c7bd1152cb33a25789a2fd60
Original-Change-Id: I46baeb1bb6f076c132e735724b094ee8a99e9257
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44917
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46974
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml

@@ -46,6 +46,27 @@
   <mssAccessorName>freq_pb_mhz</mssAccessorName>
 </attribute>
 <!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_FREQ_MCA_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The frequency of the memory controller channel. In synchronous mode,
+    this is equivalent to ATTR_FREQ_PB_MHZ. This may be independently set
+    per pair of memory channels if operating in asynchronous mode,
+    but this configuration is not anticipated. This clock drives the MCU queues,
+    and all the associated logic that drives the inputs to the DMI and reads
+    its outputs.
+  </description>
+  <valueType>uint32</valueType>
+  <enum>
+    2000 = 2000,
+    2400 = 2400
+  </enum>
+  <writeable/>
+  <platInit/>
+  <mssAccessorName>freq_mca_mhz</mssAccessorName>
+</attribute>
+<!-- ********************************************************************** -->
 <attribute>
   <id>ATTR_FREQ_O_MHZ</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>