adding iss 768 init for p9 behaviour in nmmu

Change-Id: I41d302272200ddc37276f56e238ccab8ed768163
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81386
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com>
Reviewed-by: JAKE C TRUELOVE <jtruelove@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81401
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -3164,6 +3164,23 @@
       </chip>
     </chipEcFeature>
   </attribute>
+  <!-- ********************************************************************* -->
+<attribute>
+    <id>ATTR_CHIP_EC_FEATURE_NMMU_AX1_ISS768_FIX_DIS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+       NMMU disables seg fault generation for radix access to DR=1, HV=1 with lpid !=0.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_AXONE</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
   <!-- ******************************************************************** -->
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_NMMU_PWC_DIS_DD2</id>