Add disabled bit processing for DDR PHY initial calibration

Change-Id: I5d177529dd61cc59cb89ded524698841260bef22
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31367
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69785
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml

@@ -1989,6 +1989,21 @@
         <mssAccessorName>cal_step_enable</mssAccessorName>
     </attribute>
 
+    <attribute>
+        <id>ATTR_MSS_CAL_ABORT_ON_ERROR</id>
+        <targetType>TARGET_TYPE_SYSTEM</targetType>
+        <description>
+          Whether or not to abort on the first DDR PHY calibration error.
+          Firmware should always have this set to NO. YES can be used in the
+          lab for troubleshooting, screening, etc.
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <enum>NO = 0, YES = 1</enum>
+        <mssAccessorName>cal_abort_on_error</mssAccessorName>
+    </attribute>
+
     <attribute>
         <id>ATTR_MSS_SLEW_RATE_DATA</id>
         <targetType>TARGET_TYPE_MCS</targetType>