p9_sbe_npll_setup: Enable spread spectrum before starting PLL

There's a synchronizer missing on the sscgen input of the filter
PLLs, thus any changes to that input must be made before the PLL
is taken out of reset, or the spread generator inside the PLL might
start up in a skewed state, resulting in a broken spread profile.

Thus, change the procedure to enable spread before taking the PLL
out of reset, and also make sure we never try to synchronously
enable spread.

Change-Id: Ie0e545a6baf492d394a7d63d99ba5b83a0c46423
CQ: SW457204
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71886
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71912
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>

src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C

@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -91,6 +91,13 @@ fapi2::ReturnCode p9_sbe_npll_setup(const
 
     if (l_attr_ss_filter == 0x0 )
     {
+        /*
+         * If we enable spread spectrum, do it before we drop the PLL reset
+         * to avoid glitches due to the asynchronous crossing of the control
+         * signal into the PLL core.
+         */
+        FAPI_TRY(enable_spread_spectrum_via_tod(i_target_chip));
+
         FAPI_DBG("Drop PLL test enable for Spread Spectrum PLL");
         //Setting ROOT_CTRL8 register value
         //PIB.ROOT_CTRL8.TP_SS0_PLL_TEST_EN = 0
@@ -119,8 +126,6 @@ fapi2::ReturnCode p9_sbe_npll_setup(const
                     .set_AFTER_SPREAD_ENABLE(false),
                     "ERROR:SS PLL LOCK NOT SET");
 
-        FAPI_TRY(enable_spread_spectrum_via_tod(i_target_chip));
-
         FAPI_DBG("Release SS PLL Bypass");
         //Setting ROOT_CTRL8 register value
         //PIB.ROOT_CTRL8.TP_SS0_PLL_BYPASS = 0
@@ -393,21 +398,6 @@ static fapi2::ReturnCode enable_spread_spectrum_via_tod(
                        .set_TOD_TIMER_REG(l_data),
                        "Spread Spectrum enable signal not set");
 
-    fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
-
-    FAPI_DBG("check SS PLL lock again after enabling spread spectrum");
-    //Getting PLL_LOCK_REG register value
-    FAPI_TRY(fapi2::getScom(i_target_chip,
-                            PERV_TP_PLL_LOCK_REG,
-                            l_data));
-
-    FAPI_ASSERT(l_data.getBit<0>(),
-                fapi2::SS_PLL_LOCK_ERR()
-                .set_MASTER_CHIP(i_target_chip)
-                .set_SS_PLL_READ(l_data)
-                .set_AFTER_SPREAD_ENABLE(true),
-                "ERROR:SS PLL LOCK NOT SET AFTER ENABLING SPREAD SPECTRUM");
-
 fapi_try_exit:
     return fapi2::current_err;
 }

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -8577,8 +8577,9 @@
       <chip>
         <name>ENUM_ATTR_NAME_AXONE</name>
         <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <!-- essentially... never, since synchronous spread start is broken -->
+          <value>0xAF</value>
+          <test>EQUAL</test>
         </ec>
       </chip>
     </chipEcFeature>