Move clearing of CPMMR PPM WRITE DISABLE so it called on all func cores

This HWP loops over functional cores while selecting the master. The
loop exits after it detects all of the master exs in the master quad.
The logic that clears the CPMMR WRITE DISABLE was only getting called
on the master core in this loop. I added another loop over cores
which calls this logic so this bit will be cleared on all cores.

Change-Id: I023e18db961a23cd0d1181ab558f61c8df8d4ec3
CQ: SW399710
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44975
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45006
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C

@@ -184,6 +184,15 @@ fapi2::ReturnCode p9_sbe_select_ex(
     auto l_eq_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_EQ>
                                   (fapi2::TARGET_STATE_FUNCTIONAL );
 
+    // Prior to writing to PM registers, ensure that the PPM write disable
+    // bit on the Core Power Management Mode Register is cleared for all cores
+    for (auto& core : l_core_functional_vector)
+    {
+        FAPI_DBG("Clearing WRITE_DISABLE bit in core %d", core.getChipletNumber());
+        l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_DISABLE>();
+        FAPI_TRY(fapi2::putScom(core, C_CPPM_CPMMR_CLEAR , l_data64));
+    }
+
     // Read the "FORCE_ALL" attribute
     fapi2::ATTR_SYS_FORCE_ALL_CORES_Type l_attr_force_all;
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES,
@@ -378,13 +387,6 @@ fapi2::ReturnCode p9_sbe_select_ex(
         FAPI_DBG("Scoreboard values for OCC: Core 0x%016llX  EX 0x%016llX",
                  l_core_config, l_quad_config);
 
-        // Prior to writing to PFET_DELAY register, ensure that the PPM write disable
-        // bit on the Core Power Management Mode Register is cleared
-        FAPI_DBG("Clearing WRITE_DISABLE bit in core %d", l_core_num);
-        l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_DISABLE>();
-
-        FAPI_TRY(fapi2::putScom(core, C_CPPM_CPMMR_CLEAR , l_data64));
-
         // Write the default PFET Controller Delay values for the Core
         // as it will be used for istep 4
         FAPI_DBG("Setting PFET Delays in core %d", l_core_num);