Add Write CRC attributes to xml and eff_dimm

Added ATTR_EFF_PACKAGE_RANK_MAP, ATTR_EFF_NIBBLE_MAP, and
ATTR_MSS_EFF_WR_CRC attributes.

Change-Id: Ib665e22ce755282afb012ca0df9c670770fa1dd6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45386
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Dev-Ready: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69808
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml

@@ -3250,6 +3250,21 @@
         <mssAccessorName>rtt_nom_override_disable</mssAccessorName>
     </attribute>
 
+    <attribute>
+        <id>ATTR_MSS_EFF_WR_CRC</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+          Controls ENABLE/DISABLE of Write CRC
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <enum>DISABLE = 0, ENABLE = 1</enum>
+        <mssUnits> bool </mssUnits>
+        <array> 2 </array>
+        <mssAccessorName>eff_wr_crc</mssAccessorName>
+    </attribute>
+
     <attribute>
         <id>ATTR_MSS_PHY_SEQ_REFRESH</id>
         <targetType>TARGET_TYPE_MCS</targetType>