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npu2-opencapi.c
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npu2-opencapi.c
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// SPDX-License-Identifier: Apache-2.0
/*
* Support for OpenCAPI on POWER9 NPUs
*
* This file provides support for OpenCAPI as implemented on POWER9.
*
* At present, we initialise the NPU separately from the NVLink code in npu2.c.
* As such, we don't currently support mixed NVLink and OpenCAPI configurations
* on the same NPU for machines such as Witherspoon.
*
* Procedure references in this file are to the POWER9 OpenCAPI NPU Workbook
* (IBM internal document).
*
* TODO:
* - Support for mixed NVLink and OpenCAPI on the same NPU
* - Support for link ganging (one AFU using multiple links)
* - Link reset and error handling
* - Presence detection
* - Consume HDAT NPU information
* - LPC Memory support
*
* Copyright 2013-2019 IBM Corp.
*/
#include <skiboot.h>
#include <xscom.h>
#include <io.h>
#include <timebase.h>
#include <pci.h>
#include <pci-cfg.h>
#include <pci-slot.h>
#include <interrupts.h>
#include <opal.h>
#include <opal-api.h>
#include <npu2.h>
#include <npu2-regs.h>
#include <phys-map.h>
#include <i2c.h>
#include <nvram.h>
#define NPU_IRQ_LEVELS_XSL 23
#define MAX_PE_HANDLE ((1 << 15) - 1)
#define TL_MAX_TEMPLATE 63
#define TL_RATE_BUF_SIZE 32
#define OCAPI_SLOT_NORMAL PCI_SLOT_STATE_NORMAL
#define OCAPI_SLOT_LINK PCI_SLOT_STATE_LINK
#define OCAPI_SLOT_LINK_START (OCAPI_SLOT_LINK + 1)
#define OCAPI_SLOT_LINK_WAIT (OCAPI_SLOT_LINK + 2)
#define OCAPI_SLOT_LINK_TRAINED (OCAPI_SLOT_LINK + 3)
#define OCAPI_SLOT_FRESET PCI_SLOT_STATE_FRESET
#define OCAPI_SLOT_FRESET_START (OCAPI_SLOT_FRESET + 1)
#define OCAPI_SLOT_FRESET_INIT (OCAPI_SLOT_FRESET + 2)
#define OCAPI_SLOT_FRESET_ASSERT_DELAY (OCAPI_SLOT_FRESET + 3)
#define OCAPI_SLOT_FRESET_DEASSERT_DELAY (OCAPI_SLOT_FRESET + 4)
#define OCAPI_SLOT_FRESET_DEASSERT_DELAY2 (OCAPI_SLOT_FRESET + 5)
#define OCAPI_SLOT_FRESET_INIT_DELAY (OCAPI_SLOT_FRESET + 6)
#define OCAPI_LINK_TRAINING_RETRIES 2
#define OCAPI_LINK_TRAINING_TIMEOUT 3000 /* ms */
#define OCAPI_LINK_STATE_TRAINED 0x7
enum npu2_link_training_state {
NPU2_TRAIN_DEFAULT, /* fully train the link */
NPU2_TRAIN_PRBS31, /* used for Signal Integrity testing */
NPU2_TRAIN_NONE, /* used for testing with loopback cable */
};
static enum npu2_link_training_state npu2_ocapi_training_state = NPU2_TRAIN_DEFAULT;
static const struct phb_ops npu2_opencapi_ops;
static inline uint64_t index_to_stack(uint64_t index) {
switch (index) {
case 2:
case 3:
return NPU2_STACK_STCK_1;
break;
case 4:
case 5:
return NPU2_STACK_STCK_2;
break;
default:
assert(false);
}
}
static inline uint64_t index_to_stacku(uint64_t index) {
switch (index) {
case 2:
case 3:
return NPU2_STACK_STCK_1U;
break;
case 4:
case 5:
return NPU2_STACK_STCK_2U;
break;
default:
assert(false);
}
}
static inline uint64_t index_to_block(uint64_t index) {
switch (index) {
case 2:
case 4:
return NPU2_BLOCK_OTL0;
break;
case 3:
case 5:
return NPU2_BLOCK_OTL1;
break;
default:
assert(false);
}
}
static uint64_t get_odl_status(uint32_t gcid, uint64_t index)
{
uint64_t reg, status_xscom;
status_xscom = OB_ODL_STATUS(index);
xscom_read(gcid, status_xscom, ®);
return reg;
}
static uint64_t get_odl_training_status(uint32_t gcid, uint64_t index)
{
uint64_t status_xscom, reg;
status_xscom = OB_ODL_TRAINING_STATUS(index);
xscom_read(gcid, status_xscom, ®);
return reg;
}
static uint64_t get_odl_endpoint_info(uint32_t gcid, uint64_t index)
{
uint64_t status_xscom, reg;
status_xscom = OB_ODL_ENDPOINT_INFO(index);
xscom_read(gcid, status_xscom, ®);
return reg;
}
static void disable_nvlink(uint32_t gcid, int index)
{
uint64_t phy_config_scom, reg;
switch (index) {
case 2:
case 3:
phy_config_scom = OBUS_LL0_IOOL_PHY_CONFIG;
break;
case 4:
case 5:
phy_config_scom = OBUS_LL3_IOOL_PHY_CONFIG;
break;
default:
assert(false);
}
/* Disable NV-Link link layers */
xscom_read(gcid, phy_config_scom, ®);
reg &= ~OBUS_IOOL_PHY_CONFIG_NV0_NPU_ENABLED;
reg &= ~OBUS_IOOL_PHY_CONFIG_NV1_NPU_ENABLED;
reg &= ~OBUS_IOOL_PHY_CONFIG_NV2_NPU_ENABLED;
xscom_write(gcid, phy_config_scom, reg);
}
/* Procedure 13.1.3.1 - select OCAPI vs NVLink for bricks 2-3/4-5 */
static void set_transport_mux_controls(uint32_t gcid, uint32_t scom_base,
int index, enum npu2_dev_type type)
{
/* Step 1 - Set Transport MUX controls to select correct OTL or NTL */
uint64_t reg;
uint64_t field;
/* TODO: Rework this to select for NVLink too */
assert(type == NPU2_DEV_TYPE_OPENCAPI);
prlog(PR_DEBUG, "OCAPI: %s: Setting transport mux controls\n", __func__);
/* Optical IO Transport Mux Config for Bricks 0-2 and 4-5 */
reg = npu2_scom_read(gcid, scom_base, NPU2_MISC_OPTICAL_IO_CFG0,
NPU2_MISC_DA_LEN_8B);
switch (index) {
case 0:
case 1:
/* not valid for OpenCAPI */
assert(false);
break;
case 2: /* OTL1.0 */
field = GETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_NDLMUX_BRK0TO2, reg);
field &= ~0b100;
reg = SETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_NDLMUX_BRK0TO2, reg,
field);
field = GETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_OCMUX_BRK0TO1, reg);
field |= 0b10;
reg = SETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_OCMUX_BRK0TO1, reg,
field);
break;
case 3: /* OTL1.1 */
field = GETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_NDLMUX_BRK0TO2, reg);
field &= ~0b010;
reg = SETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_NDLMUX_BRK0TO2, reg,
field);
field = GETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_OCMUX_BRK0TO1, reg);
field |= 0b01;
reg = SETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_OCMUX_BRK0TO1, reg,
field);
break;
case 4: /* OTL2.0 */
field = GETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_OCMUX_BRK4TO5, reg);
field |= 0b10;
reg = SETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_OCMUX_BRK4TO5, reg,
field);
break;
case 5: /* OTL2.1 */
field = GETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_OCMUX_BRK4TO5, reg);
field |= 0b01;
reg = SETFIELD(NPU2_MISC_OPTICAL_IO_CFG0_OCMUX_BRK4TO5, reg,
field);
break;
default:
assert(false);
}
npu2_scom_write(gcid, scom_base, NPU2_MISC_OPTICAL_IO_CFG0,
NPU2_MISC_DA_LEN_8B, reg);
/*
* PowerBus Optical Miscellaneous Config Register - select
* OpenCAPI for b4/5 and A-Link for b3
*/
xscom_read(gcid, PU_IOE_PB_MISC_CFG, ®);
switch (index) {
case 0:
case 1:
case 2:
case 3:
break;
case 4:
reg = SETFIELD(PU_IOE_PB_MISC_CFG_SEL_04_NPU_NOT_PB, reg, 1);
break;
case 5:
reg = SETFIELD(PU_IOE_PB_MISC_CFG_SEL_05_NPU_NOT_PB, reg, 1);
break;
}
xscom_write(gcid, PU_IOE_PB_MISC_CFG, reg);
}
static void assert_odl_reset(uint32_t gcid, int index)
{
uint64_t reg, config_xscom;
config_xscom = OB_ODL_CONFIG(index);
/* Reset ODL */
reg = OB_ODL_CONFIG_RESET;
reg = SETFIELD(OB_ODL_CONFIG_VERSION, reg, 0b000001);
reg = SETFIELD(OB_ODL_CONFIG_TRAIN_MODE, reg, 0b0110);
reg = SETFIELD(OB_ODL_CONFIG_SUPPORTED_MODES, reg, 0b0010);
reg |= OB_ODL_CONFIG_X4_BACKOFF_ENABLE;
reg = SETFIELD(OB_ODL_CONFIG_PHY_CNTR_LIMIT, reg, 0b1111);
reg |= OB_ODL_CONFIG_DEBUG_ENABLE;
reg = SETFIELD(OB_ODL_CONFIG_FWD_PROGRESS_TIMER, reg, 0b0110);
xscom_write(gcid, config_xscom, reg);
}
static void deassert_odl_reset(uint32_t gcid, int index)
{
uint64_t reg, config_xscom;
config_xscom = OB_ODL_CONFIG(index);
xscom_read(gcid, config_xscom, ®);
reg &= ~OB_ODL_CONFIG_RESET;
xscom_write(gcid, config_xscom, reg);
}
static void enable_odl_phy_mux(uint32_t gcid, int index)
{
uint64_t reg;
uint64_t phy_config_scom;
prlog(PR_DEBUG, "OCAPI: %s: Enabling ODL to PHY MUXes\n", __func__);
/* Step 2 - Enable MUXes for ODL to PHY connection */
switch (index) {
case 2:
case 3:
phy_config_scom = OBUS_LL0_IOOL_PHY_CONFIG;
break;
case 4:
case 5:
phy_config_scom = OBUS_LL3_IOOL_PHY_CONFIG;
break;
default:
assert(false);
}
/*
* ODL must be in reset when enabling.
* It stays in reset until the link is trained
*/
assert_odl_reset(gcid, index);
/* PowerBus OLL PHY Training Config Register */
xscom_read(gcid, phy_config_scom, ®);
/*
* Enable ODL to use shared PHYs
*
* On obus3, OTL0 is connected to ODL1 (and OTL1 to ODL0), so
* even if it may look odd at first, we do want to enable ODL0
* for links 2 and 5
*/
switch (index) {
case 2:
case 5:
reg |= OBUS_IOOL_PHY_CONFIG_ODL0_ENABLED;
break;
case 3:
case 4:
reg |= OBUS_IOOL_PHY_CONFIG_ODL1_ENABLED;
break;
}
/*
* Based on the platform, we may have to activate an extra mux
* to connect the ODL to the right set of lanes.
*
* FIXME: to be checked once we have merged with nvlink
* code. Need to verify that it's a platform parameter and not
* slot-dependent
*/
if (platform.ocapi->odl_phy_swap)
reg |= OBUS_IOOL_PHY_CONFIG_ODL_PHY_SWAP;
else
reg &= ~OBUS_IOOL_PHY_CONFIG_ODL_PHY_SWAP;
/* Disable A-Link link layers */
reg &= ~OBUS_IOOL_PHY_CONFIG_LINK0_OLL_ENABLED;
reg &= ~OBUS_IOOL_PHY_CONFIG_LINK1_OLL_ENABLED;
xscom_write(gcid, phy_config_scom, reg);
}
static void disable_alink_fp(uint32_t gcid)
{
uint64_t reg = 0;
prlog(PR_DEBUG, "OCAPI: %s: Disabling A-Link framer/parsers\n", __func__);
/* Step 3 - Disable A-Link framers/parsers */
/* TODO: Confirm if needed on OPAL system */
reg |= PU_IOE_PB_FP_CFG_FP0_FMR_DISABLE;
reg |= PU_IOE_PB_FP_CFG_FP0_PRS_DISABLE;
reg |= PU_IOE_PB_FP_CFG_FP1_FMR_DISABLE;
reg |= PU_IOE_PB_FP_CFG_FP1_PRS_DISABLE;
xscom_write(gcid, PU_IOE_PB_FP01_CFG, reg);
xscom_write(gcid, PU_IOE_PB_FP23_CFG, reg);
xscom_write(gcid, PU_IOE_PB_FP45_CFG, reg);
xscom_write(gcid, PU_IOE_PB_FP67_CFG, reg);
}
static void enable_xsl_clocks(uint32_t gcid, uint32_t scom_base, int index)
{
/* Step 5 - Enable Clocks in XSL */
prlog(PR_DEBUG, "OCAPI: %s: Enable clocks in XSL\n", __func__);
npu2_scom_write(gcid, scom_base, NPU2_REG_OFFSET(index_to_stack(index),
NPU2_BLOCK_XSL,
NPU2_XSL_WRAP_CFG),
NPU2_MISC_DA_LEN_8B, NPU2_XSL_WRAP_CFG_XSLO_CLOCK_ENABLE);
}
#define CQ_CTL_STATUS_TIMEOUT 10 /* milliseconds */
static int set_fence_control(uint32_t gcid, uint32_t scom_base,
int index, uint8_t status)
{
int stack, block;
uint64_t reg, status_field;
uint8_t status_val;
uint64_t fence_control;
uint64_t timeout = mftb() + msecs_to_tb(CQ_CTL_STATUS_TIMEOUT);
stack = index_to_stack(index);
block = index_to_block(index);
fence_control = NPU2_REG_OFFSET(stack, NPU2_BLOCK_CTL,
block == NPU2_BLOCK_OTL0 ?
NPU2_CQ_CTL_FENCE_CONTROL_0 :
NPU2_CQ_CTL_FENCE_CONTROL_1);
reg = SETFIELD(NPU2_CQ_CTL_FENCE_CONTROL_REQUEST_FENCE, 0ull, status);
npu2_scom_write(gcid, scom_base, fence_control,
NPU2_MISC_DA_LEN_8B, reg);
/* Wait for fence status to update */
if (index_to_block(index) == NPU2_BLOCK_OTL0)
status_field = NPU2_CQ_CTL_STATUS_BRK0_AM_FENCED;
else
status_field = NPU2_CQ_CTL_STATUS_BRK1_AM_FENCED;
do {
reg = npu2_scom_read(gcid, scom_base,
NPU2_REG_OFFSET(index_to_stack(index),
NPU2_BLOCK_CTL,
NPU2_CQ_CTL_STATUS),
NPU2_MISC_DA_LEN_8B);
status_val = GETFIELD(status_field, reg);
if (status_val == status)
return OPAL_SUCCESS;
time_wait_ms(1);
} while (tb_compare(mftb(), timeout) == TB_ABEFOREB);
/**
* @fwts-label OCAPIFenceStatusTimeout
* @fwts-advice The NPU fence status did not update as expected. This
* could be the result of a firmware or hardware bug. OpenCAPI
* functionality could be broken.
*/
prlog(PR_ERR,
"OCAPI: Fence status for brick %d stuck: expected 0x%x, got 0x%x\n",
index, status, status_val);
return OPAL_HARDWARE;
}
static void set_npcq_config(uint32_t gcid, uint32_t scom_base, int index)
{
uint64_t reg, stack, block;
prlog(PR_DEBUG, "OCAPI: %s: Set NPCQ Config\n", __func__);
/* Step 6 - Set NPCQ configuration */
/* CQ_CTL Misc Config Register #0 */
stack = index_to_stack(index);
block = index_to_block(index);
/* Enable OTL */
npu2_scom_write(gcid, scom_base, NPU2_OTL_CONFIG0(stack, block),
NPU2_MISC_DA_LEN_8B, NPU2_OTL_CONFIG0_EN);
set_fence_control(gcid, scom_base, index, 0b01);
reg = npu2_scom_read(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_CTL,
NPU2_CQ_CTL_MISC_CFG),
NPU2_MISC_DA_LEN_8B);
/* Set OCAPI mode */
reg |= NPU2_CQ_CTL_MISC_CFG_CONFIG_OCAPI_MODE;
if (block == NPU2_BLOCK_OTL0)
reg |= NPU2_CQ_CTL_MISC_CFG_CONFIG_OTL0_ENABLE;
else
reg |= NPU2_CQ_CTL_MISC_CFG_CONFIG_OTL1_ENABLE;
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_CTL,
NPU2_CQ_CTL_MISC_CFG),
NPU2_MISC_DA_LEN_8B, reg);
/* NPU Fenced */
set_fence_control(gcid, scom_base, index, 0b11);
/* NPU Half Fenced */
set_fence_control(gcid, scom_base, index, 0b10);
/* CQ_DAT Misc Config Register #1 */
reg = npu2_scom_read(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_DAT,
NPU2_CQ_DAT_MISC_CFG),
NPU2_MISC_DA_LEN_8B);
/* Set OCAPI mode for bricks 2-5 */
reg |= NPU2_CQ_DAT_MISC_CFG_CONFIG_OCAPI_MODE;
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_DAT,
NPU2_CQ_DAT_MISC_CFG),
NPU2_MISC_DA_LEN_8B, reg);
/* CQ_SM Misc Config Register #0 */
for (block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; block++) {
reg = npu2_scom_read(gcid, scom_base,
NPU2_REG_OFFSET(stack, block,
NPU2_CQ_SM_MISC_CFG0),
NPU2_MISC_DA_LEN_8B);
/* Set OCAPI mode for bricks 2-5 */
reg |= NPU2_CQ_SM_MISC_CFG0_CONFIG_OCAPI_MODE;
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, block,
NPU2_CQ_SM_MISC_CFG0),
NPU2_MISC_DA_LEN_8B, reg);
}
}
static void enable_xsl_xts_interfaces(uint32_t gcid, uint32_t scom_base, int index)
{
uint64_t reg;
prlog(PR_DEBUG, "OCAPI: %s: Enable XSL-XTS Interfaces\n", __func__);
/* Step 7 - Enable XSL-XTS interfaces */
/* XTS Config Register - Enable XSL-XTS interface */
reg = npu2_scom_read(gcid, scom_base, NPU2_XTS_CFG, NPU2_MISC_DA_LEN_8B);
reg |= NPU2_XTS_CFG_OPENCAPI;
npu2_scom_write(gcid, scom_base, NPU2_XTS_CFG, NPU2_MISC_DA_LEN_8B, reg);
/* XTS Config2 Register - Enable XSL1/2 */
reg = npu2_scom_read(gcid, scom_base, NPU2_XTS_CFG2, NPU2_MISC_DA_LEN_8B);
switch (index_to_stack(index)) {
case NPU2_STACK_STCK_1:
reg |= NPU2_XTS_CFG2_XSL1_ENA;
break;
case NPU2_STACK_STCK_2:
reg |= NPU2_XTS_CFG2_XSL2_ENA;
break;
}
npu2_scom_write(gcid, scom_base, NPU2_XTS_CFG2, NPU2_MISC_DA_LEN_8B, reg);
}
static void enable_sm_allocation(uint32_t gcid, uint32_t scom_base, int index)
{
uint64_t reg, block;
int stack = index_to_stack(index);
prlog(PR_DEBUG, "OCAPI: %s: Enable State Machine Allocation\n", __func__);
/* Step 8 - Enable state-machine allocation */
/* Low-Water Marks Registers - Enable state machine allocation */
for (block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; block++) {
reg = npu2_scom_read(gcid, scom_base,
NPU2_REG_OFFSET(stack, block,
NPU2_LOW_WATER_MARKS),
NPU2_MISC_DA_LEN_8B);
reg |= NPU2_LOW_WATER_MARKS_ENABLE_MACHINE_ALLOC;
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, block,
NPU2_LOW_WATER_MARKS),
NPU2_MISC_DA_LEN_8B, reg);
}
}
static void enable_pb_snooping(uint32_t gcid, uint32_t scom_base, int index)
{
uint64_t reg, block;
int stack = index_to_stack(index);
prlog(PR_DEBUG, "OCAPI: %s: Enable PowerBus snooping\n", __func__);
/* Step 9 - Enable PowerBus snooping */
/* CQ_SM Misc Config Register #0 - Enable PowerBus snooping */
for (block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; block++) {
reg = npu2_scom_read(gcid, scom_base,
NPU2_REG_OFFSET(stack, block,
NPU2_CQ_SM_MISC_CFG0),
NPU2_MISC_DA_LEN_8B);
reg |= NPU2_CQ_SM_MISC_CFG0_CONFIG_ENABLE_PBUS;
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, block,
NPU2_CQ_SM_MISC_CFG0),
NPU2_MISC_DA_LEN_8B, reg);
}
}
static void brick_config(uint32_t gcid, uint32_t scom_base, int index)
{
/*
* We assume at this point that the PowerBus Hotplug Mode Control
* register is correctly set by Hostboot
*/
disable_nvlink(gcid, index);
set_transport_mux_controls(gcid, scom_base, index,
NPU2_DEV_TYPE_OPENCAPI);
enable_odl_phy_mux(gcid, index);
disable_alink_fp(gcid);
enable_xsl_clocks(gcid, scom_base, index);
set_npcq_config(gcid, scom_base, index);
enable_xsl_xts_interfaces(gcid, scom_base, index);
enable_sm_allocation(gcid, scom_base, index);
enable_pb_snooping(gcid, scom_base, index);
}
/* Procedure 13.1.3.4 - Brick to PE Mapping */
static void pe_config(struct npu2_dev *dev)
{
/* We currently use a fixed PE assignment per brick */
uint64_t val, reg;
val = NPU2_MISC_BRICK_BDF2PE_MAP_ENABLE;
val = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_PE, val, NPU2_OCAPI_PE(dev));
val = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_BDF, val, 0);
reg = NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC,
NPU2_MISC_BRICK0_BDF2PE_MAP0 +
(dev->brick_index * 0x18));
npu2_write(dev->npu, reg, val);
}
/* Procedure 13.1.3.5 - TL Configuration */
static void tl_config(uint32_t gcid, uint32_t scom_base, uint64_t index)
{
uint64_t reg;
uint64_t stack = index_to_stack(index);
uint64_t block = index_to_block(index);
prlog(PR_DEBUG, "OCAPI: %s: TL Configuration\n", __func__);
/* OTL Config 0 Register */
reg = 0;
/* OTL Enable */
reg |= NPU2_OTL_CONFIG0_EN;
/* Block PE Handle from ERAT Index */
reg |= NPU2_OTL_CONFIG0_BLOCK_PE_HANDLE;
/* OTL Brick ID */
reg = SETFIELD(NPU2_OTL_CONFIG0_BRICKID, reg, index - 2);
/* ERAT Hash 0 */
reg = SETFIELD(NPU2_OTL_CONFIG0_ERAT_HASH_0, reg, 0b011001);
/* ERAT Hash 1 */
reg = SETFIELD(NPU2_OTL_CONFIG0_ERAT_HASH_1, reg, 0b000111);
/* ERAT Hash 2 */
reg = SETFIELD(NPU2_OTL_CONFIG0_ERAT_HASH_2, reg, 0b101100);
/* ERAT Hash 3 */
reg = SETFIELD(NPU2_OTL_CONFIG0_ERAT_HASH_3, reg, 0b100110);
npu2_scom_write(gcid, scom_base, NPU2_OTL_CONFIG0(stack, block),
NPU2_MISC_DA_LEN_8B, reg);
/* OTL Config 1 Register */
reg = 0;
/*
* We leave Template 1-3 bits at 0 to force template 0 as required
* for unknown devices.
*
* Template 0 Transmit Rate is set to most conservative setting which
* will always be supported. Other Template Transmit rates are left
* unset and will be set later by OS.
*/
reg = SETFIELD(NPU2_OTL_CONFIG1_TX_TEMP0_RATE, reg, 0b1111);
/* Extra wait cycles TXI-TXO */
reg = SETFIELD(NPU2_OTL_CONFIG1_TX_DRDY_WAIT, reg, 0b001);
/* Minimum Frequency to Return TLX Credits to AFU */
reg = SETFIELD(NPU2_OTL_CONFIG1_TX_CRET_FREQ, reg, 0b001);
/* Frequency to add age to Transmit Requests */
reg = SETFIELD(NPU2_OTL_CONFIG1_TX_AGE_FREQ, reg, 0b11000);
/* Response High Priority Threshold */
reg = SETFIELD(NPU2_OTL_CONFIG1_TX_RS2_HPWAIT, reg, 0b011011);
/* 4-slot Request High Priority Threshold */
reg = SETFIELD(NPU2_OTL_CONFIG1_TX_RQ4_HPWAIT, reg, 0b011011);
/* 6-slot Request High Priority */
reg = SETFIELD(NPU2_OTL_CONFIG1_TX_RQ6_HPWAIT, reg, 0b011011);
/* Stop the OCAPI Link on Uncorrectable Error
* TODO: Confirm final value - disabled for debug */
npu2_scom_write(gcid, scom_base, NPU2_OTL_CONFIG1(stack, block),
NPU2_MISC_DA_LEN_8B, reg);
/* TLX Credit Configuration Register */
reg = 0;
/* VC0/VC3/DCP0/DCP1 credits to send to AFU */
reg = SETFIELD(NPU2_OTL_TLX_CREDITS_VC0_CREDITS, reg, 0x40);
reg = SETFIELD(NPU2_OTL_TLX_CREDITS_VC3_CREDITS, reg, 0x40);
reg = SETFIELD(NPU2_OTL_TLX_CREDITS_DCP0_CREDITS, reg, 0x80);
reg = SETFIELD(NPU2_OTL_TLX_CREDITS_DCP1_CREDITS, reg, 0x80);
npu2_scom_write(gcid, scom_base, NPU2_OTL_TLX_CREDITS(stack, block),
NPU2_MISC_DA_LEN_8B, reg);
}
/* Detect Nimbus DD2.0 and DD2.01 */
static int get_nimbus_level(void)
{
struct proc_chip *chip = next_chip(NULL);
if (chip && chip->type == PROC_CHIP_P9_NIMBUS)
return chip->ec_level & 0xff;
return -1;
}
/* Procedure 13.1.3.6 - Address Translation Configuration */
static void address_translation_config(uint32_t gcid, uint32_t scom_base,
uint64_t index)
{
int chip_level;
uint64_t reg;
uint64_t stack = index_to_stack(index);
prlog(PR_DEBUG, "OCAPI: %s: Address Translation Configuration\n", __func__);
/* PSL_SCNTL_A0 Register */
/*
* ERAT shared between multiple AFUs
*
* The workbook has this bit around the wrong way from the hardware.
*
* TODO: handle correctly with link ganging
*/
reg = npu2_scom_read(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_XSL,
NPU2_XSL_PSL_SCNTL_A0),
NPU2_MISC_DA_LEN_8B);
reg |= NPU2_XSL_PSL_SCNTL_A0_MULTI_AFU_DIAL;
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_XSL,
NPU2_XSL_PSL_SCNTL_A0),
NPU2_MISC_DA_LEN_8B, reg);
chip_level = get_nimbus_level();
if (chip_level == 0x20) {
/*
* Errata HW408041 (section 15.1.10 of NPU workbook)
* "RA mismatch when both tlbie and checkout response
* are seen in same cycle"
*/
/* XSL_GP Register - Bloom Filter Disable */
reg = npu2_scom_read(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_XSL, NPU2_XSL_GP),
NPU2_MISC_DA_LEN_8B);
/* To update XSL_GP, we must first write a magic value to it */
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_XSL, NPU2_XSL_GP),
NPU2_MISC_DA_LEN_8B, 0x0523790323000000UL);
reg &= ~NPU2_XSL_GP_BLOOM_FILTER_ENABLE;
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_XSL, NPU2_XSL_GP),
NPU2_MISC_DA_LEN_8B, reg);
}
if (chip_level == 0x20 || chip_level == 0x21) {
/*
* DD2.0/2.1 EOA Bug. Fixed in DD2.2
*/
reg = 0x32F8000000000001UL;
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_XSL,
NPU2_XSL_DEF),
NPU2_MISC_DA_LEN_8B, reg);
}
}
/* TODO: Merge this with NVLink implementation - we don't use the npu2_bar
* wrapper for the PHY BARs yet */
static void write_bar(uint32_t gcid, uint32_t scom_base, uint64_t reg,
uint64_t addr, uint64_t size)
{
uint64_t val;
int block;
switch (NPU2_REG(reg)) {
case NPU2_PHY_BAR:
val = SETFIELD(NPU2_PHY_BAR_ADDR, 0ul, addr >> 21);
val = SETFIELD(NPU2_PHY_BAR_ENABLE, val, 1);
break;
case NPU2_NTL0_BAR:
case NPU2_NTL1_BAR:
val = SETFIELD(NPU2_NTL_BAR_ADDR, 0ul, addr >> 16);
val = SETFIELD(NPU2_NTL_BAR_SIZE, val, ilog2(size >> 16));
val = SETFIELD(NPU2_NTL_BAR_ENABLE, val, 1);
break;
case NPU2_GENID_BAR:
val = SETFIELD(NPU2_GENID_BAR_ADDR, 0ul, addr >> 16);
val = SETFIELD(NPU2_GENID_BAR_ENABLE, val, 1);
break;
default:
val = 0ul;
}
for (block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; block++) {
npu2_scom_write(gcid, scom_base, NPU2_REG_OFFSET(0, block, reg),
NPU2_MISC_DA_LEN_8B, val);
prlog(PR_DEBUG, "OCAPI: Setting BAR %llx to %llx\n",
NPU2_REG_OFFSET(0, block, reg), val);
}
}
static void setup_global_mmio_bar(uint32_t gcid, uint32_t scom_base,
uint64_t reg[])
{
uint64_t addr, size;
prlog(PR_DEBUG, "OCAPI: patching up PHY0 bar, %s\n", __func__);
phys_map_get(gcid, NPU_PHY, 0, &addr, &size);
write_bar(gcid, scom_base,
NPU2_REG_OFFSET(NPU2_STACK_STCK_2, 0, NPU2_PHY_BAR),
addr, size);
prlog(PR_DEBUG, "OCAPI: patching up PHY1 bar, %s\n", __func__);
phys_map_get(gcid, NPU_PHY, 1, &addr, &size);
write_bar(gcid, scom_base,
NPU2_REG_OFFSET(NPU2_STACK_STCK_1, 0, NPU2_PHY_BAR),
addr, size);
prlog(PR_DEBUG, "OCAPI: setup global mmio, %s\n", __func__);
phys_map_get(gcid, NPU_REGS, 0, &addr, &size);
write_bar(gcid, scom_base,
NPU2_REG_OFFSET(NPU2_STACK_STCK_0, 0, NPU2_PHY_BAR),
addr, size);
reg[0] = addr;
reg[1] = size;
}
/* Procedure 13.1.3.8 - AFU MMIO Range BARs */
static void setup_afu_mmio_bars(uint32_t gcid, uint32_t scom_base,
struct npu2_dev *dev)
{
uint64_t stack = index_to_stack(dev->brick_index);
uint64_t offset = index_to_block(dev->brick_index) == NPU2_BLOCK_OTL0 ?
NPU2_NTL0_BAR : NPU2_NTL1_BAR;
uint64_t pa_offset = index_to_block(dev->brick_index) == NPU2_BLOCK_OTL0 ?
NPU2_CQ_CTL_MISC_MMIOPA0_CONFIG :
NPU2_CQ_CTL_MISC_MMIOPA1_CONFIG;
uint64_t addr, size, reg;
prlog(PR_DEBUG, "OCAPI: %s: Setup AFU MMIO BARs\n", __func__);
phys_map_get(gcid, NPU_OCAPI_MMIO, dev->brick_index, &addr, &size);
prlog(PR_DEBUG, "OCAPI: AFU MMIO set to %llx, size %llx\n", addr, size);
write_bar(gcid, scom_base, NPU2_REG_OFFSET(stack, 0, offset), addr,
size);
dev->bars[0].npu2_bar.base = addr;
dev->bars[0].npu2_bar.size = size;
reg = SETFIELD(NPU2_CQ_CTL_MISC_MMIOPA_ADDR, 0ull, addr >> 16);
reg = SETFIELD(NPU2_CQ_CTL_MISC_MMIOPA_SIZE, reg, ilog2(size >> 16));
prlog(PR_DEBUG, "OCAPI: PA translation %llx\n", reg);
npu2_scom_write(gcid, scom_base,
NPU2_REG_OFFSET(stack, NPU2_BLOCK_CTL,
pa_offset),
NPU2_MISC_DA_LEN_8B, reg);
}
/* Procedure 13.1.3.9 - AFU Config BARs */
static void setup_afu_config_bars(uint32_t gcid, uint32_t scom_base,
struct npu2_dev *dev)
{
uint64_t stack = index_to_stack(dev->brick_index);
int stack_num = stack - NPU2_STACK_STCK_0;
uint64_t addr, size;
prlog(PR_DEBUG, "OCAPI: %s: Setup AFU Config BARs\n", __func__);
phys_map_get(gcid, NPU_GENID, stack_num, &addr, &size);
prlog(PR_DEBUG, "OCAPI: Assigning GENID BAR: %016llx\n", addr);
write_bar(gcid, scom_base, NPU2_REG_OFFSET(stack, 0, NPU2_GENID_BAR),
addr, size);
dev->bars[1].npu2_bar.base = addr;
dev->bars[1].npu2_bar.size = size;
}
static void otl_enabletx(uint32_t gcid, uint32_t scom_base,
struct npu2_dev *dev)
{
uint64_t stack = index_to_stack(dev->brick_index);
uint64_t block = index_to_block(dev->brick_index);
uint64_t reg;
/* OTL Config 2 Register */
/* Transmit Enable */
OCAPIDBG(dev, "Enabling TX\n");
reg = 0;
reg |= NPU2_OTL_CONFIG2_TX_SEND_EN;
npu2_scom_write(gcid, scom_base, NPU2_OTL_CONFIG2(stack, block),
NPU2_MISC_DA_LEN_8B, reg);
reg = npu2_scom_read(gcid, scom_base, NPU2_OTL_VC_CREDITS(stack, block),
NPU2_MISC_DA_LEN_8B);
OCAPIDBG(dev, "credit counter: %llx\n", reg);
/* TODO: Abort if credits are zero */
}
static uint8_t get_reset_pin(struct npu2_dev *dev)
{
uint8_t pin;
switch (dev->brick_index) {
case 2:
pin = platform.ocapi->i2c_reset_brick2;
break;
case 3:
pin = platform.ocapi->i2c_reset_brick3;
break;
case 4:
pin = platform.ocapi->i2c_reset_brick4;
break;
case 5:
pin = platform.ocapi->i2c_reset_brick5;
break;
default:
assert(false);
}
return pin;
}
static void assert_adapter_reset(struct npu2_dev *dev)
{
uint8_t pin, data;
int rc;
pin = get_reset_pin(dev);
/*
* set the i2c reset pin in output mode
*
* On the 9554 device, register 3 is the configuration
* register and a pin is in output mode if its value is 0
*/
lock(&dev->npu->i2c_lock);
dev->npu->i2c_pin_mode &= ~pin;
data = dev->npu->i2c_pin_mode;
rc = i2c_request_send(dev->npu->i2c_port_id_ocapi,
platform.ocapi->i2c_reset_addr, SMBUS_WRITE,
0x3, 1,
&data, sizeof(data), 120);
if (rc)
goto err;
/* register 1 controls the signal, reset is active low */
dev->npu->i2c_pin_wr_state &= ~pin;
data = dev->npu->i2c_pin_wr_state;
rc = i2c_request_send(dev->npu->i2c_port_id_ocapi,
platform.ocapi->i2c_reset_addr, SMBUS_WRITE,
0x1, 1,
&data, sizeof(data), 120);
if (rc)
goto err;
unlock(&dev->npu->i2c_lock);
return;
err:
unlock(&dev->npu->i2c_lock);
/**
* @fwts-label OCAPIDeviceResetFailed
* @fwts-advice There was an error attempting to send
* a reset signal over I2C to the OpenCAPI device.
*/
OCAPIERR(dev, "Error writing I2C reset signal: %d\n", rc);
}
static void deassert_adapter_reset(struct npu2_dev *dev)
{
uint8_t pin, data;
int rc;
pin = get_reset_pin(dev);
lock(&dev->npu->i2c_lock);
dev->npu->i2c_pin_wr_state |= pin;
data = dev->npu->i2c_pin_wr_state;
rc = i2c_request_send(dev->npu->i2c_port_id_ocapi,
platform.ocapi->i2c_reset_addr, SMBUS_WRITE,
0x1, 1,
&data, sizeof(data), 120);
unlock(&dev->npu->i2c_lock);
if (rc) {
/**
* @fwts-label OCAPIDeviceResetFailed
* @fwts-advice There was an error attempting to send
* a reset signal over I2C to the OpenCAPI device.
*/
OCAPIERR(dev, "Error writing I2C reset signal: %d\n", rc);
}
}
static void setup_perf_counters(struct npu2_dev *dev)
{
uint64_t addr, reg, link;
/*
* setup the DLL perf counters to check CRC errors detected by
* the NPU or the adapter.
*
* Counter 0: link 0/ODL0, CRC error detected by ODL
* Counter 1: link 0/ODL0, CRC error detected by DLx
* Counter 2: link 1/ODL1, CRC error detected by ODL
* Counter 3: link 1/ODL1, CRC error detected by DLx
*/
if ((dev->brick_index == 2) || (dev->brick_index == 5))
link = 0;
else
link = 1;
addr = OB_DLL_PERF_MONITOR_CONFIG(dev->brick_index);
xscom_read(dev->npu->chip_id, addr, ®);
if (link == 0) {
reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_ENABLE, reg,
OB_DLL_PERF_MONITOR_CONFIG_LINK0);
reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_ENABLE >> 2, reg,
OB_DLL_PERF_MONITOR_CONFIG_LINK0);
} else {
reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_ENABLE >> 4, reg,
OB_DLL_PERF_MONITOR_CONFIG_LINK1);
reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_ENABLE >> 6, reg,
OB_DLL_PERF_MONITOR_CONFIG_LINK1);
}
reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_SIZE, reg,
OB_DLL_PERF_MONITOR_CONFIG_SIZE16);
xscom_write(dev->npu->chip_id,
OB_DLL_PERF_MONITOR_CONFIG(dev->brick_index), reg);
OCAPIDBG(dev, "perf counter config %llx = %llx\n", addr, reg);
addr = OB_DLL_PERF_MONITOR_SELECT(dev->brick_index);
xscom_read(dev->npu->chip_id, addr, ®);
reg = SETFIELD(OB_DLL_PERF_MONITOR_SELECT_COUNTER >> (link * 16),
reg, OB_DLL_PERF_MONITOR_SELECT_CRC_ODL);
reg = SETFIELD(OB_DLL_PERF_MONITOR_SELECT_COUNTER >> ((link * 16) + 8),
reg, OB_DLL_PERF_MONITOR_SELECT_CRC_DLX);
xscom_write(dev->npu->chip_id, addr, reg);
OCAPIDBG(dev, "perf counter select %llx = %llx\n", addr, reg);
}
static void check_perf_counters(struct npu2_dev *dev)
{
uint64_t addr, reg, link0, link1;
addr = OB_DLL_PERF_COUNTER0(dev->brick_index);
xscom_read(dev->npu->chip_id, addr, ®);
link0 = GETFIELD(PPC_BITMASK(0, 31), reg);
link1 = GETFIELD(PPC_BITMASK(32, 63), reg);
if (link0 || link1)