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npu2.c
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npu2.c
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// SPDX-License-Identifier: Apache-2.0
/*
* NPU - NVlink and OpenCAPI
*
* Copyright 2013-2019 IBM Corp.
*/
#include <skiboot.h>
#include <io.h>
#include <timebase.h>
#include <pci-cfg.h>
#include <pci.h>
#include <pci-slot.h>
#include <pci-virt.h>
#include <opal.h>
#include <opal-api.h>
#include <cpu.h>
#include <device.h>
#include <ccan/str/str.h>
#include <ccan/array_size/array_size.h>
#include <affinity.h>
#include <npu2.h>
#include <lock.h>
#include <xscom.h>
#include <bitutils.h>
#include <chip.h>
#include <phys-map.h>
#include <nvram.h>
#include <xscom-p9-regs.h>
#include <phb4.h>
#include <cache-p9.h>
#define VENDOR_CAP_START 0x80
#define VENDOR_CAP_END 0x90
#define VENDOR_CAP_LEN 0x10
#define VENDOR_CAP_VERSION 0x01
#define VENDOR_CAP_PCI_DEV_OFFSET 0x0d
/*
* NPU2 BAR layout definition. We have 3 stacks and each of them
* contains 2 bricks. So every NPU2 has 6 bricks in total. There are 2
* PHY BARs and each of them is shared by 3 bricks. Every brick has
* one NTL BAR and two bricks share one GENID BAR. There is also a
* global MMIO BAR. We only expose DL and GENID BARs to the OS and all
* other BARs will be hidden in skiboot.
*
* Before the global MMIO BAR is configured, scom is the only way to
* access the BAR registers. At NPU2 PHB probing time, we rely on scom
* to assign all BARs until the global MMIO BAR is established.
*
* We need to access 4 SM registers in the same stack in order to
* configure one particular BAR.
*/
/* Set a specific flag in the vendor config space */
void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag)
{
ndev->nvlink.link_flags |= flag;
PCI_VIRT_CFG_INIT_RO(ndev->nvlink.pvd, VENDOR_CAP_START +
VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags);
}
void npu2_clear_link_flag(struct npu2_dev *ndev, uint8_t flag)
{
ndev->nvlink.link_flags &= ~flag;
PCI_VIRT_CFG_INIT_RO(ndev->nvlink.pvd, VENDOR_CAP_START +
VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags);
}
static inline void npu2_ioda_sel(struct npu2 *p, uint32_t table,
uint32_t index, bool autoinc)
{
out_be64(p->regs + NPU2_ATS_IODA_TBL,
(autoinc ? NPU2_ATS_IODA_TBL_AUTOINC : 0ul) |
SETFIELD(NPU2_ATS_IODA_TBL_SELECT, 0ul, table) |
SETFIELD(NPU2_ATS_IODA_TBL_INDEX, 0ul, index));
}
static struct npu2_dev *npu2_bdf_to_dev(struct npu2 *p,
uint32_t bdfn)
{
struct pci_virt_device *pvd;
/* All emulated devices are attached to root bus */
if (bdfn & ~0xff)
return NULL;
pvd = pci_virt_find_device(&p->phb_nvlink, bdfn);
if (pvd)
return pvd->data;
return NULL;
}
static inline void npu2_get_bar(uint32_t gcid, struct npu2_bar *bar)
{
phys_map_get(gcid, bar->type, bar->index, &bar->base, &bar->size);
}
static void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar)
{
uint64_t reg, val;
int enabled;
reg = NPU2_REG_OFFSET(0, NPU2_BLOCK_SM_0, bar->reg);
val = npu2_read(p, reg);
switch (NPU2_REG(bar->reg)) {
case NPU2_PHY_BAR:
bar->base = GETFIELD(NPU2_PHY_BAR_ADDR, val) << 21;
enabled = GETFIELD(NPU2_PHY_BAR_ENABLE, val);
if (NPU2_REG_STACK(reg) == NPU2_STACK_STCK_2)
/* This is the global MMIO BAR */
bar->size = 0x1000000;
else
bar->size = 0x200000;
break;
case NPU2_NTL0_BAR:
case NPU2_NTL1_BAR:
bar->base = GETFIELD(NPU2_NTL_BAR_ADDR, val) << 16;
enabled = GETFIELD(NPU2_NTL_BAR_ENABLE, val);
bar->size = 0x10000 << GETFIELD(NPU2_NTL_BAR_SIZE, val);
break;
case NPU2_GENID_BAR:
bar->base = GETFIELD(NPU2_GENID_BAR_ADDR, val) << 16;
enabled = GETFIELD(NPU2_GENID_BAR_ENABLE, val);
bar->size = 0x20000;
break;
default:
bar->base = 0ul;
enabled = 0;
bar->size = 0;
break;
}
bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED, bar->flags, enabled);
}
static void npu2_write_bar(struct npu2 *p,
struct npu2_bar *bar,
uint32_t gcid,
uint32_t scom)
{
uint64_t reg, val, enable = !!(bar->flags & NPU2_BAR_FLAG_ENABLED);
int block;
switch (NPU2_REG(bar->reg)) {
case NPU2_PHY_BAR:
val = SETFIELD(NPU2_PHY_BAR_ADDR, 0ul, bar->base >> 21);
val = SETFIELD(NPU2_PHY_BAR_ENABLE, val, enable);
break;
case NPU2_NTL0_BAR:
case NPU2_NTL1_BAR:
val = SETFIELD(NPU2_NTL_BAR_ADDR, 0ul, bar->base >> 16);
val = SETFIELD(NPU2_NTL_BAR_ENABLE, val, enable);
val = SETFIELD(NPU2_NTL_BAR_SIZE, val, 1);
break;
case NPU2_GENID_BAR:
val = SETFIELD(NPU2_GENID_BAR_ADDR, 0ul, bar->base >> 16);
val = SETFIELD(NPU2_GENID_BAR_ENABLE, val, enable);
break;
default:
val = 0ul;
}
for (block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; block++) {
reg = NPU2_REG_OFFSET(0, block, bar->reg);
if (p)
npu2_write(p, reg, val);
else
npu2_scom_write(gcid, scom, reg, NPU2_MISC_DA_LEN_8B, val);
}
}
/* Trap for PCI command (0x4) to enable or disable device's BARs */
static int64_t npu2_cfg_write_cmd(void *dev,
struct pci_cfg_reg_filter *pcrf __unused,
uint32_t offset, uint32_t size,
uint32_t *data, bool write)
{
struct pci_virt_device *pvd = dev;
struct npu2_dev *ndev = pvd->data;
struct npu2_bar *ntl_npu_bar, *genid_npu_bar;
bool enabled;
if (!write)
return OPAL_PARTIAL;
if (offset != PCI_CFG_CMD)
return OPAL_PARAMETER;
if (size != 1 && size != 2 && size != 4)
return OPAL_PARAMETER;
/*
* Enable or disable NTL and GENID BAR. Two bricks share
* one GENID BAR, which is exposed via the first brick.
*/
enabled = !!(*data & PCI_CFG_CMD_MEM_EN);
ntl_npu_bar = &ndev->bars[0].npu2_bar;
genid_npu_bar = &ndev->bars[1].npu2_bar;
ntl_npu_bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED, ntl_npu_bar->flags, enabled);
npu2_write_bar(ndev->npu, ntl_npu_bar, 0, 0);
/*
* Enable/disable the GENID BAR. Two bricks share one GENID
* BAR which is exposed via the first brick so we need to
* track the enables separately.
*/
if (NPU2DEV_BRICK(ndev))
genid_npu_bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED1, genid_npu_bar->flags,
enabled);
else
genid_npu_bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED0, genid_npu_bar->flags,
enabled);
/* Enable the BAR if either device requests it enabled, otherwise disable it */
genid_npu_bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED, genid_npu_bar->flags,
!!(genid_npu_bar->flags & (NPU2_BAR_FLAG_ENABLED0 |
NPU2_BAR_FLAG_ENABLED1)));
npu2_write_bar(ndev->npu, genid_npu_bar, 0, 0);
return OPAL_PARTIAL;
}
static int64_t npu2_cfg_read_bar(struct npu2_dev *dev __unused,
struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t size,
uint32_t *data)
{
struct npu2_pcie_bar *bar = (struct npu2_pcie_bar *) pcrf->data;
if (!(bar->flags & NPU2_PCIE_BAR_FLAG_TRAPPED))
return OPAL_PARTIAL;
if ((size != 4) ||
(offset != pcrf->start && offset != pcrf->start + 4))
return OPAL_PARAMETER;
if (bar->flags & NPU2_PCIE_BAR_FLAG_SIZE_HI)
*data = bar->npu2_bar.size >> 32;
else
*data = bar->npu2_bar.size;
bar->flags &= ~(NPU2_PCIE_BAR_FLAG_TRAPPED | NPU2_PCIE_BAR_FLAG_SIZE_HI);
return OPAL_SUCCESS;
}
static int64_t npu2_cfg_write_bar(struct npu2_dev *dev,
struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t size,
uint32_t data)
{
struct npu2_pcie_bar *bar = (struct npu2_pcie_bar *) pcrf->data;
struct npu2_bar old_bar, *npu2_bar = &bar->npu2_bar;
if ((size != 4) ||
(offset != pcrf->start && offset != pcrf->start + 4))
return OPAL_PARAMETER;
/* Return BAR size on next read */
if (data == 0xffffffff) {
bar->flags |= NPU2_PCIE_BAR_FLAG_TRAPPED;
if (offset == pcrf->start + 4)
bar->flags |= NPU2_PCIE_BAR_FLAG_SIZE_HI;
return OPAL_SUCCESS;
}
if (offset == pcrf->start) {
npu2_bar->base &= 0xffffffff00000000UL;
npu2_bar->base |= (data & 0xfffffff0);
} else {
npu2_bar->base &= 0x00000000ffffffffUL;
npu2_bar->base |= ((uint64_t)data << 32);
if (NPU2_REG(npu2_bar->reg) == NPU2_GENID_BAR && NPU2DEV_BRICK(dev))
npu2_bar->base -= 0x10000;
old_bar.reg = npu2_bar->reg;
npu2_read_bar(dev->npu, &old_bar);
/* Only allow changing the base address if the BAR is not enabled */
if ((npu2_bar->flags & NPU2_BAR_FLAG_ENABLED) &&
(npu2_bar->base != old_bar.base)) {
npu2_bar->base = old_bar.base;
return OPAL_HARDWARE;
}
npu2_write_bar(dev->npu, &bar->npu2_bar, 0, 0);
}
/* To update the config cache */
return OPAL_PARTIAL;
}
static int64_t npu2_dev_cfg_bar(void *dev, struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t len, uint32_t *data,
bool write)
{
struct pci_virt_device *pvd = dev;
struct npu2_dev *ndev = (struct npu2_dev *) pvd->data;
if (write)
return npu2_cfg_write_bar(ndev, pcrf, offset, len, *data);
return npu2_cfg_read_bar(ndev, pcrf, offset, len, data);
}
static int64_t npu2_dev_cfg_exp_devcap(void *dev,
struct pci_cfg_reg_filter *pcrf __unused,
uint32_t offset, uint32_t size,
uint32_t *data, bool write)
{
struct pci_virt_device *pvd = dev;
struct npu2_dev *ndev = pvd->data;
int rc;
assert(write);
if ((size != 2) || (offset & 1)) {
/* Short config writes are not supported */
prlog(PR_ERR, "NPU%d: Unsupported write to pcie control register\n",
ndev->nvlink.phb->opal_id);
return OPAL_PARAMETER;
}
if (*data & PCICAP_EXP_DEVCTL_FUNC_RESET)
npu2_dev_procedure_reset(ndev);
rc = purge_l2_l3_caches();
if (rc)
return rc;
return OPAL_PARTIAL;
}
#define NPU2_CFG_READ(size, type) \
static int64_t npu2_cfg_read##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type *data) \
{ \
uint32_t val; \
int64_t ret; \
\
ret = pci_virt_cfg_read(phb, bdfn, offset, \
sizeof(*data), &val); \
*data = (type)val; \
return ret; \
}
#define NPU2_CFG_WRITE(size, type) \
static int64_t npu2_cfg_write##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type data) \
{ \
uint32_t val = data; \
int64_t ret; \
\
ret = pci_virt_cfg_write(phb, bdfn, offset, \
sizeof(data), val); \
return ret; \
}
NPU2_CFG_READ(8, u8);
NPU2_CFG_READ(16, u16);
NPU2_CFG_READ(32, u32);
NPU2_CFG_WRITE(8, u8);
NPU2_CFG_WRITE(16, u16);
NPU2_CFG_WRITE(32, u32);
static int __npu2_dev_bind_pci_dev(struct phb *phb __unused,
struct pci_device *pd,
void *data)
{
struct npu2_dev *dev = data;
struct dt_node *pci_dt_node;
char *pcislot;
/* Ignore non-nvidia PCI devices */
if ((pd->vdid & 0xffff) != 0x10de)
return 0;
/* Find the PCI device's slot location */
for (pci_dt_node = pd->dn;
pci_dt_node && !dt_find_property(pci_dt_node, "ibm,loc-code");
pci_dt_node = pci_dt_node->parent);
if (!pci_dt_node)
return 0;
pcislot = (char *)dt_prop_get(pci_dt_node, "ibm,loc-code");
NPU2DEVDBG(dev, "Comparing GPU '%s' and NPU2 '%s'\n",
pcislot, dev->nvlink.slot_label);
if (streq(pcislot, dev->nvlink.slot_label))
return 1;
return 0;
}
static int64_t npu2_gpu_bridge_sec_bus_reset(void *dev,
struct pci_cfg_reg_filter *pcrf __unused,
uint32_t offset, uint32_t len,
uint32_t *data, bool write)
{
struct pci_device *pd = dev;
struct pci_device *gpu;
struct phb *npphb;
struct npu2 *npu;
struct dt_node *np;
struct npu2_dev *ndev;
int i;
assert(write);
if ((len != 2) || (offset & 1)) {
/* Short config writes are not supported */
PCIERR(pd->phb, pd->bdfn,
"Unsupported write to bridge control register\n");
return OPAL_PARAMETER;
}
gpu = list_top(&pd->children, struct pci_device, link);
if (gpu && (*data & PCI_CFG_BRCTL_SECONDARY_RESET)) {
int64_t rc;
dt_for_each_compatible(dt_root, np, "ibm,power9-npu-pciex") {
npphb = pci_get_phb(dt_prop_get_cell(np,
"ibm,opal-phbid", 1));
if (!npphb || npphb->phb_type != phb_type_npu_v2)
continue;
npu = phb_to_npu2_nvlink(npphb);
for (i = 0; i < npu->total_devices; ++i) {
ndev = &npu->devices[i];
if (ndev->nvlink.pd == gpu)
npu2_dev_procedure_reset(ndev);
}
}
rc = purge_l2_l3_caches();
if (rc)
return rc;
}
return OPAL_PARTIAL;
}
static void npu2_dev_bind_pci_dev(struct npu2_dev *dev)
{
struct phb *phb;
uint32_t i;
if (dev->nvlink.pd)
return;
for (i = 0; i < 64; i++) {
if (dev->npu->phb_nvlink.opal_id == i)
continue;
phb = pci_get_phb(i);
if (!phb)
continue;
dev->nvlink.pd = pci_walk_dev(phb, NULL, __npu2_dev_bind_pci_dev, dev);
if (dev->nvlink.pd) {
dev->nvlink.phb = phb;
/* Found the device, set the bit in config space */
npu2_set_link_flag(dev, NPU2_DEV_PCI_LINKED);
/*
* We define a custom sec bus reset handler for a slot
* with an NVLink-connected GPU to prevent HMIs which
* will otherwise happen if we reset GPU before
* resetting NVLinks.
*/
if (dev->nvlink.pd->parent &&
dev->nvlink.pd->parent->slot)
pci_add_cfg_reg_filter(dev->nvlink.pd->parent,
PCI_CFG_BRCTL, 2,
PCI_REG_FLAG_WRITE,
npu2_gpu_bridge_sec_bus_reset);
return;
}
}
NPU2DEVINF(dev, "No PCI device found for slot '%s'\n",
dev->nvlink.slot_label);
}
static struct lock pci_npu_phandle_lock = LOCK_UNLOCKED;
static void npu2_append_phandle(struct dt_node *dn,
u32 phandle)
{
struct dt_property *prop;
uint32_t *npu_phandles;
size_t len;
/*
* Use a lock to make sure no one else has a reference to an
* ibm,npu property (this assumes this is the only function
* that holds a reference to it)
*/
lock(&pci_npu_phandle_lock);
/* This function shouldn't be called unless ibm,npu exists */
prop = (struct dt_property *)dt_require_property(dn, "ibm,npu", -1);
/* Need to append to the properties */
len = prop->len + sizeof(*npu_phandles);
dt_resize_property(&prop, len);
prop->len = len;
npu_phandles = (uint32_t *)prop->prop;
npu_phandles[len / sizeof(*npu_phandles) - 1] = phandle;
unlock(&pci_npu_phandle_lock);
}
static struct dt_node *npu2_create_memory_dn(uint64_t addr, uint64_t size)
{
struct dt_node *mem;
static u32 chip_id = 255;
mem = dt_find_by_name_addr(dt_root, "memory", addr);
if (mem)
return mem;
mem = dt_new_addr(dt_root, "memory", addr);
if (!mem)
return NULL;
dt_add_property_string(mem, "device_type", "memory");
dt_add_property_string(mem, "compatible", "ibm,coherent-device-memory");
dt_add_property_u64s(mem, "reg", addr, size);
dt_add_property_cells(mem, "ibm,chip-id", chip_id);
dt_add_property_u64s(mem, "linux,usable-memory", addr, 0);
dt_add_property_cells(mem, "ibm,associativity", 4, chip_id, chip_id, chip_id, chip_id);
chip_id--;
assert(chip_id);
return mem;
}
/* There are potentially multiple links per GPU, so lookup the GPU memory based
* on bdfn. */
static void npu2_get_gpu_base(struct npu2_dev *ndev, uint64_t *addr, uint64_t *size)
{
struct npu2 *p = ndev->npu;
int group;
group = PCI_DEV(ndev->bdfn);
phys_map_get(ndev->npu->chip_id, p->gpu_map_type, group, addr, size);
}
static void npu2_dn_fixup_gmb(struct dt_node *pd_dn, struct npu2_dev *ndev)
{
uint64_t gpu_base, gpu_size, gta;
struct dt_node *mem_dn;
npu2_get_gpu_base(ndev, &gpu_base, &gpu_size);
mem_dn = npu2_create_memory_dn(gpu_base, gpu_size);
assert(mem_dn);
dt_add_property_cells(pd_dn, "memory-region", mem_dn->phandle);
/* Coral mode address compression. This is documented in Figure 3.5
* "P9->GPU RA Compression (Coral) of the NPU2 workbook". */
gta = ((gpu_base >> 42) & 0x1) << 42;
gta |= ((gpu_base >> 45) & 0x3) << 43;
gta |= ((gpu_base >> 49) & 0x3) << 45;
gta |= gpu_base & ((1UL << 43) - 1);
dt_add_property_u64s(pd_dn, "ibm,device-tgt-addr", gta);
}
static int npu2_assign_gmb(struct npu2_dev *ndev)
{
struct npu2 *p = ndev->npu;
int peers, mode;
uint32_t bdfn;
uint64_t base, size, reg, val, gmb;
/* Need to work out number of link peers. This amount to
* working out the maximum function number. So work start at
* the highest bdfn (fn = 6) and count back until we find a
* npu2_dev. */
for (bdfn = (ndev->bdfn & ~0x7) | NPU2_LINKS_PER_CHIP;
PCI_FUNC(bdfn) != 0x7; bdfn = (bdfn & ~0x7) | (PCI_FUNC(bdfn) - 1))
if (npu2_bdf_to_dev(p, bdfn))
break;
peers = PCI_FUNC(bdfn);
npu2_get_gpu_base(ndev, &base, &size);
NPU2DBG(p, "Setting BAR region dt:%llx\n", base);
val = SETFIELD(NPU2_MEM_BAR_EN, 0ULL, 1);
val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, val, base >> (63-14));
val = SETFIELD(NPU2_MEM_BAR_GROUP, val, base >> (63-18));
val = SETFIELD(NPU2_MEM_BAR_CHIP, val, base >> (63-21));
val = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, val, base >> (63-33));
val = SETFIELD(NPU2_MEM_BAR_POISON, val, 1);
val = SETFIELD(NPU2_MEM_BAR_GRANULE, val, 0);
/* We don't know how much memory the GPU has, so we may as well just
* pass the whole aperture through at this point. */
val = SETFIELD(NPU2_MEM_BAR_BAR_SIZE, val, ilog2(size >> 30));
switch (peers) {
case 0:
mode = 0;
break;
case 1:
mode = 1;
break;
case 2:
mode = 3;
break;
case 3:
mode = 6;
break;
case 5:
mode = 10;
break;
default:
/* Hardware does not support this configuration */
assert(0);
}
mode += PCI_FUNC(ndev->bdfn);
val = SETFIELD(NPU2_MEM_BAR_MODE, val, mode);
gmb = NPU2_GPU0_MEM_BAR;
if (NPU2DEV_BRICK(ndev))
gmb = NPU2_GPU1_MEM_BAR;
reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev),
NPU2_BLOCK_SM_0, gmb);
npu2_write(p, reg, val);
reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev),
NPU2_BLOCK_SM_1, gmb);
npu2_write(p, reg, val);
reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev),
NPU2_BLOCK_SM_2, gmb);
npu2_write(p, reg, val);
reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev),
NPU2_BLOCK_SM_3, gmb);
npu2_write(p, reg, val);
return 0;
}
static int npu2_dn_fixup(struct phb *phb,
struct pci_device *pd,
void *data __unused)
{
struct npu2 *p = phb_to_npu2_nvlink(phb);
struct npu2_dev *dev;
uint32_t speed;
const char *label;
dev = npu2_bdf_to_dev(p, pd->bdfn);
assert(dev);
if (dev->nvlink.phb || dev->nvlink.pd)
return 0;
npu2_assign_gmb(dev);
npu2_dn_fixup_gmb(pd->dn, dev);
dt_add_property_cells(pd->dn, "ibm,nvlink", dev->dt_node->phandle);
/*
* NVLink supports multiple speeds and device drivers need to know what
* speed has been set by firmware. Hostboot does the inits that set the
* link speed and tell us via HDAT and we need to copy that from the
* link node.
*/
speed = dt_prop_get_u32_def(dev->dt_node, "nvidia,link-speed", 0xff);
if (speed != 0xff)
dt_add_property_cells(pd->dn, "ibm,nvlink-speed", speed);
/*
* NPU2 devices have a slot label that indicates which GPU slot
* this NPU is connected to. Add a location code to the NVlink
* device node based on the slot label.
*/
label = dt_prop_get_def(dev->dt_node, "ibm,slot-label", NULL);
if (!label) {
/**
* @fwts-label NPUNoPHBSlotLabel
* @fwts-advice No GPU/NPU2 slot information was found.
* NVLink2 functionality will not work.
*/
prlog(PR_ERR, "NPU: Cannot find GPU slot information\n");
return 0;
}
dt_add_property_string(pd->dn, "ibm,loc-code", label);
dev->nvlink.slot_label = label;
/*
* Bind the emulated PCI device with the real one, which can't
* be done until the PCI devices are populated. Once the real
* PCI device is identified, we also need fix the device-tree
* for it
*/
npu2_dev_bind_pci_dev(dev);
if (dev->nvlink.phb && dev->nvlink.pd && dev->nvlink.pd->dn) {
if (dt_find_property(dev->nvlink.pd->dn, "ibm,npu"))
npu2_append_phandle(dev->nvlink.pd->dn, pd->dn->phandle);
else
dt_add_property_cells(dev->nvlink.pd->dn, "ibm,npu", pd->dn->phandle);
dt_add_property_cells(pd->dn, "ibm,gpu", dev->nvlink.pd->dn->phandle);
dev->nvlink.gpu_bdfn = dev->nvlink.pd->bdfn;
}
return 0;
}
static int npu2_links_per_gpu(struct phb *phb,
struct pci_device *pd,
void *data)
{
struct npu2 *p = phb_to_npu2_nvlink(phb);
struct npu2_dev *dev;
int *nlinks = (int *)data;
dev = npu2_bdf_to_dev(p, pd->bdfn);
assert(dev);
if (dev->nvlink.phb && dev->nvlink.pd && dev->nvlink.pd->dn) {
const struct dt_property *prop;
int n;
/* The link count is the number of phandles in "ibm,npu" */
prop = dt_find_property(dev->nvlink.pd->dn, "ibm,npu");
if (!prop)
return 0;
/* Count could vary by gpu, so find the max */
n = prop->len / sizeof(uint32_t);
if (n > *nlinks)
*nlinks = n;
}
return 0;
}
static void npu2_phb_fixup_scominit(struct dt_node *dn, int links_per_gpu)
{
uint32_t gcid = dt_get_chip_id(dn);
uint64_t val, mask;
/*
* MRBSP settings for 2- and 3-link GPU systems. These can improve
* GPU peer-to-peer fully ordered write performance.
*/
if (links_per_gpu == 3) {
val = PPC_BIT(30) | PPC_BIT(34) | PPC_BIT(36) | PPC_BIT(37) |
PPC_BIT(44) | PPC_BIT(45);
mask = PPC_BITMASK(28,39) | PPC_BITMASK(44,47);
} else if (links_per_gpu == 2) {
val = PPC_BIT(46) | PPC_BIT(47);
mask = PPC_BITMASK(44,47);
} else
return;
xscom_write_mask(gcid, 0x50110c0, val, mask);
xscom_write_mask(gcid, 0x50112c0, val, mask);
xscom_write_mask(gcid, 0x50114c0, val, mask);
}
static void npu2_phb_final_fixup(struct phb *phb)
{
int links_per_gpu = 0;
struct dt_node *np;
pci_walk_dev(phb, NULL, npu2_dn_fixup, NULL);
/*
* Now that the emulated devices are bound to the real ones, we can
* determine links_per_gpu and do some final init.
*/
pci_walk_dev(phb, NULL, npu2_links_per_gpu, &links_per_gpu);
dt_for_each_compatible(dt_root, np, "ibm,power9-npu")
npu2_phb_fixup_scominit(np, links_per_gpu);
}
static void npu2_init_ioda_cache(struct npu2 *p)
{
/* TVT */
memset(p->tve_cache, 0, sizeof(p->tve_cache));
}
static int64_t npu2_ioda_reset(struct phb *phb, bool purge)
{
struct npu2 *p = phb_to_npu2_nvlink(phb);
uint32_t i;
if (purge) {
NPU2DBG(p, "Purging all IODA tables...\n");
npu2_init_ioda_cache(p);
}
/* TVT */
npu2_ioda_sel(p, NPU2_ATS_IODA_TBL_TVT, 0, true);
for (i = 0; i < ARRAY_SIZE(p->tve_cache); i++)
out_be64(p->regs + NPU2_ATS_IODA_DATA, p->tve_cache[i]);
return OPAL_SUCCESS;
}
static void npu2_write_mcd(struct npu2 *p, uint64_t pcb_addr, uint64_t addr,
uint64_t size)
{
uint64_t val;
NPU2DBG(p, "Setting MCD addr:%llx\n", pcb_addr);
assert(is_pow2(size));
val = MCD_BANK_CN_VALID;
val = SETFIELD(MCD_BANK_CN_SIZE, val, (size >> 25) - 1);
val = SETFIELD(MCD_BANK_CN_ADDR, val, addr >> 25);
xscom_write(p->chip_id, pcb_addr, val);
}
static void npu2_mcd_init(struct npu2 *p)
{
int i;
uint64_t size, addr, gpu_min_addr, gpu_max_addr, total_size;
/* Init memory cache directory (MCD) registers. */
phys_map_get(p->chip_id, p->gpu_map_type, NPU2_LINKS_PER_CHIP - 1,
&gpu_min_addr, NULL);
phys_map_get(p->chip_id, p->gpu_map_type, 0, &gpu_max_addr, &size);
gpu_max_addr += size;
/* We assume GPU memory is contiguous from the first possible GPU to the
* last and that the size is the same so best to check that. */
for (i = 0; i < NPU2_LINKS_PER_CHIP; i++) {
uint64_t tmp;
phys_map_get(p->chip_id, p->gpu_map_type, i, &addr, &tmp);
assert((addr >= gpu_min_addr) && (addr + tmp <= gpu_max_addr));
assert(tmp == size);
}
/* We have two MCDs, so if neccessary we can split the region covered
* across both if total_size is not a power of two. */
total_size = gpu_max_addr - gpu_min_addr;
size = 1ull << ilog2(total_size);
/* Allocate the biggest chunk first as we assume gpu_max_addr has the
* highest alignment. */
addr = gpu_max_addr - size;
npu2_write_mcd(p, MCD0_BANK0_CN3, addr, size);
total_size -= size;
if (total_size) {
/* total_size was not a power of two, but the remainder should
* be if all GPUs were assigned the same size. */
assert(is_pow2(total_size));
size = 1ull << ilog2(total_size);
addr -= size;
assert(addr <= gpu_min_addr);
npu2_write_mcd(p, MCD1_BANK0_CN3, addr, size);
}
}
static void npu2_hw_init(struct npu2 *p)
{
uint64_t reg, val;
int s, b;
npu2_ioda_reset(&p->phb_nvlink, false);
/* Enable XTS retry mode */
val = npu2_read(p, NPU2_XTS_CFG);
npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO);
val = npu2_read(p, NPU2_XTS_CFG2);
npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA);
/*
* There are three different ways we configure the MCD and memory map.
* 1) Old way
* Skiboot configures the MCD and puts GPUs at 4TB and below
* 2) New way with MCD
* Hostboot configures the MCD and skiboot puts GPU at 4TB and above
* 3) New way without MCD
* No one configures the MCD and skiboot puts GPU at 4TB and below
*
* 1) Will go away evenutally as it's a configuration that can
* cause an xstop or data integrity problems. We are keeping
* it around to support existing hostboot. Print error
* message if used.
* 2) Is for smaller memory configurations and will be used
* initially for GPUs on Witherspoon. Supports only to
* 512GB of memory and 4 GPUs per socket.
* 3) Is for fully populated configurations of 4TB of memory
* and 6GPUs per socket. May have performance impacts.
*
* The different configurations can be detected via the following scoms:
* 1) 0x5011c0c bit 2 = 1, 0x5011c0a bits 42:48 = 0
* 2) 0x5011c0c bit 2 = 1, 0x5011c0a bits 42:48 = 7
* 3) 0x5011c0c bit 2 = 0, 0x5011c0a bits 42:48 = 0
*/
/* Get 0x05011c0c bit 2 = 1 */
xscom_read(p->chip_id, PB_CENT_HP_MODE_CURR, &val);
if ((val & PB_CFG_CHG_RATE_GP_MASTER) != 0) {
/* Get 0x05011c0a bits 42:48 */
xscom_read(p->chip_id, PB_CENT_MODE, &val);
if (GETFIELD(PB_CFG_CHIP_ADDR_EXTENSION_MASK_CENT, val) == 0) {
/* 1) */
NPU2DBG(p, "Using old memory map + MCD enabled in skiboot\n");
NPU2ERR(p, "!!! Old firmware detected. Update hostboot for new MCD mapping !!!\n");
p->gpu_map_type = GPU_MEM_4T_DOWN;
npu2_mcd_init(p);
} else if (GETFIELD(PB_CFG_CHIP_ADDR_EXTENSION_MASK_CENT, val) == 7) {
/* 2) */
NPU2DBG(p, "Using small memory map + MCD enabled\n");
p->gpu_map_type = GPU_MEM_4T_UP;
} else
NPU2ERR(p, "!!! Unsupported NPU2 configuration. "
"0x%llx!!!\n", val);
} else {
/* 3) */
NPU2DBG(p, "Using large memory map + MCD disabled\n");
p->gpu_map_type = GPU_MEM_4T_DOWN;
}
/* Static initialization of every relaxed-ordering cfg[2] register */
val = NPU2_RELAXED_ORDERING_CMD_CL_DMA_W |
NPU2_RELAXED_ORDERING_CMD_CL_DMA_W_HP |
NPU2_RELAXED_ORDERING_CMD_CL_DMA_INJ |
NPU2_RELAXED_ORDERING_CMD_PR_DMA_INJ |
NPU2_RELAXED_ORDERING_CMD_DMA_PR_W |
NPU2_RELAXED_ORDERING_CMD_CL_RD_NC_F0 |
NPU2_RELAXED_ORDERING_SOURCE4_RDENA;
for (s = NPU2_STACK_STCK_0; s <= NPU2_STACK_STCK_2; s++) {
for (b = NPU2_BLOCK_SM_0; b <= NPU2_BLOCK_SM_3; b++) {
reg = NPU2_REG_OFFSET(s, b, NPU2_RELAXED_ORDERING_CFG(2));
npu2_write(p, reg, val);
}
}
}
static int64_t npu2_map_pe_dma_window_real(struct phb *phb,
uint64_t pe_num,
uint16_t window_id,
uint64_t pci_start_addr __unused,
uint64_t pci_mem_size __unused)
{
struct npu2 *p = phb_to_npu2_nvlink(phb);
uint64_t tve;
/* Sanity check. Each PE has one corresponding TVE */
if (pe_num >= NPU2_MAX_PE_NUM ||
window_id != pe_num)
return OPAL_PARAMETER;
if (pci_mem_size) {
/* GPUs need to be able to access the MMIO memory space as well.
* On POWER9 this is above the top of ram so disable the TVT
* range check allowing access to all memory addresses. */
tve = 0;
} else {
/* Disable */
tve = PPC_BIT(51);
}
npu2_ioda_sel(p, NPU2_ATS_IODA_TBL_TVT, window_id, false);
out_be64(p->regs + NPU2_ATS_IODA_DATA, tve);
p->tve_cache[window_id] = tve;
return OPAL_SUCCESS;
}
static int64_t npu2_map_pe_dma_window(struct phb *phb,
uint64_t pe_num,
uint16_t window_id,
uint16_t tce_levels,
uint64_t tce_table_addr,
uint64_t tce_table_size,
uint64_t tce_page_size)
{
struct npu2 *p = phb_to_npu2_nvlink(phb);
uint64_t tts_encoded;
uint64_t data64 = 0;
/* Sanity check. Each PE has one corresponding TVE */
if (pe_num >= NPU2_MAX_PE_NUM ||
window_id != pe_num)
return OPAL_PARAMETER;
/*
* Special condition, zero TCE table size used to disable
* the TVE.
*/
if (!tce_table_size) {
npu2_ioda_sel(p, NPU2_ATS_IODA_TBL_TVT, window_id, false);