-
Notifications
You must be signed in to change notification settings - Fork 134
/
npu.c
1701 lines (1428 loc) · 48.6 KB
/
npu.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* Copyright 2013-2015 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <skiboot.h>
#include <io.h>
#include <timebase.h>
#include <pci.h>
#include <pci-cfg.h>
#include <pci-virt.h>
#include <pci-slot.h>
#include <interrupts.h>
#include <opal.h>
#include <opal-api.h>
#include <cpu.h>
#include <device.h>
#include <ccan/str/str.h>
#include <ccan/array_size/array_size.h>
#include <ccan/build_assert/build_assert.h>
#include <affinity.h>
#include <npu-regs.h>
#include <npu.h>
#include <xscom.h>
#include <string.h>
/*
* Terminology:
*
* Brick - A group of either 8 TX or 8 RX lanes
* Link - A group of 8 TX and 8 RX lanes
*
* Each link is represented in system software as an emulated PCI
* device. Garrison has two chips each with 4 links, therefore there
* are 8 emulated PCI devices in total.
*
* +----------------------------------------------------------------+
* | PBCQ3 (SCOM Base Address 0x2012c00) |
* | PHB3 (SCOM Base Address 0x9012c00) |
* +----------------------------------------------------------------+
* |||||||| ||||||||
* |||||||| ||||||||
* |||||||| ||||||||
* |||||||| ||||||||
* +----------------------------------------------------------------+
* | PCIe x8 |
* +----------------------------------------------------------------+
* | GPU0 |
* +--------------------------------+-------------------------------+
* | NV Link 1 | NV Link 0 |
* +---------------+----------------+---------------+---------------+
* | RX | TX | RX | TX |
* +---------------+----------------+---------------+---------------+
* |||||||| |||||||| |||||||| ||||||||
* |||||||| |||||||| |||||||| ||||||||
* |||||||| |||||||| |||||||| ||||||||
* |||||||| |||||||| |||||||| ||||||||
* +---------------+----------------+---------------+---------------+
* | TX | RX | TX | RX |
* +---------------+----------------+---------------+---------------+
* | Lanes [0:7] PHY 0 Lanes [8:15] |
* | SCOM Base Address 0x8000080008010c3f |
* +--------------------------------+-------------------------------+
* | Link 0 NDL/NTL | Link 1 NTL/NDL |
* | SCOM Base Address 0x8013c00 | SCOM Base Address 0x8013c40 |
* +--------------------------------+-------------------------------+
* | |
* | Address Translation/AT (shared for all links) |
* | SCOM Base Address 0x8013d80 |
* | |
* +--------------------------------+-------------------------------+
* | Link 3 NDL/NTL | Link 4 NTL/NDL |
* | SCOM Base Address 0x8013d00 | SCOM Base Address 0x8013d40 |
* +--------------------------------+-------------------------------+
* | Lanes [8:15] PHY 1 Lanes [0:7] |
* | SCOM Base Address 0x8000080008010c7f |
* +---------------+----------------+---------------+---------------+
* | TX | RX | TX | RX |
* +---------------+----------------+---------------+---------------+
* |||||||| |||||||| |||||||| ||||||||
* |||||||| |||||||| |||||||| ||||||||
* |||||||| |||||||| |||||||| ||||||||
* |||||||| |||||||| |||||||| ||||||||
* +---------------+----------------+---------------+---------------+
* | RX | TX | RX | TX |
* +---------------+----------------+---------------+---------------+
* | NV Link 2 | NV Link 3 |
* +--------------------------------+-------------------------------+
* | GPU1 |
* +----------------------------------------------------------------+
* | PCIe x8 |
* +----------------------------------------------------------------+
* |||||||| ||||||||
* |||||||| ||||||||
* |||||||| ||||||||
* |||||||| ||||||||
* +----------------------------------------------------------------+
* | PHB2 (SCOM Base Address 0x9012800) |
* | PBCQ2 (SCOM Base Address 0x2012800) |
* +----------------------------------------------------------------+
*
*/
static struct npu_dev_cap *npu_dev_find_capability(struct npu_dev *dev,
uint16_t id);
#define OPAL_NPU_VERSION 0x02
#define PCIE_CAP_START 0x40
#define PCIE_CAP_END 0x80
#define VENDOR_CAP_START 0x80
#define VENDOR_CAP_END 0x90
#define VENDOR_CAP_PCI_DEV_OFFSET 0x0d
/* Returns the scom base for the given link index */
static uint64_t npu_link_scom_base(struct dt_node *dn, uint32_t scom_base,
int index)
{
struct dt_node *link;
uint32_t link_index;
char namebuf[32];
snprintf(namebuf, sizeof(namebuf), "link@%x", index);
link = dt_find_by_name(dn, namebuf);
assert(link);
link_index = dt_prop_get_u32(link, "ibm,npu-link-index");
return scom_base + (link_index * NPU_LINK_SIZE);
}
static uint64_t get_bar_size(uint64_t bar)
{
return (1 << GETFIELD(NX_MMIO_BAR_SIZE, bar)) * 0x10000;
}
/* Update the changes of the device BAR to link BARs */
static void npu_dev_bar_update(uint32_t gcid, struct npu_dev_bar *bar,
bool enable)
{
uint64_t val;
if (!bar->xscom)
return;
val = bar->base;
val = SETFIELD(NX_MMIO_BAR_SIZE, val, ilog2(bar->size / 0x10000));
if (enable)
val |= NX_MMIO_BAR_ENABLE;
xscom_write(gcid, bar->xscom, val);
}
/* Trap for PCI command (0x4) to enable or disable device's BARs */
static int64_t npu_dev_cfg_write_cmd(void *dev,
struct pci_cfg_reg_filter *pcrf __unused,
uint32_t offset, uint32_t size,
uint32_t *data, bool write)
{
struct pci_virt_device *pvd = dev;
struct npu_dev *ndev = pvd->data;
bool enable;
if (!write)
return OPAL_PARTIAL;
if (offset != PCI_CFG_CMD)
return OPAL_PARAMETER;
if (size != 1 && size != 2 && size != 4)
return OPAL_PARAMETER;
/* Update device BARs and link BARs will be syncrhonized
* with hardware automatically.
*/
enable = !!(*data & PCI_CFG_CMD_MEM_EN);
npu_dev_bar_update(ndev->npu->chip_id, &ndev->bar, enable);
/* Normal path to update PCI config buffer */
return OPAL_PARTIAL;
}
/*
* Trap for memory BARs: 0xFF's should be written to BAR register
* prior to getting its size.
*/
static int64_t npu_dev_cfg_bar_read(struct npu_dev *dev __unused,
struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t size,
uint32_t *data)
{
struct npu_dev_bar *bar = (struct npu_dev_bar *)(pcrf->data);
/* Revert to normal path if we weren't trapped for BAR size */
if (!bar->trapped)
return OPAL_PARTIAL;
if (offset != pcrf->start &&
offset != pcrf->start + 4)
return OPAL_PARAMETER;
if (size != 4)
return OPAL_PARAMETER;
bar->trapped = false;
*data = bar->bar_sz;
return OPAL_SUCCESS;
}
static int64_t npu_dev_cfg_bar_write(struct npu_dev *dev,
struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t size,
uint32_t data)
{
struct pci_virt_device *pvd = dev->pvd;
struct npu_dev_bar *bar = (struct npu_dev_bar *)(pcrf->data);
uint32_t pci_cmd;
if (offset != pcrf->start &&
offset != pcrf->start + 4)
return OPAL_PARAMETER;
if (size != 4)
return OPAL_PARAMETER;
/* Return BAR size on next read */
if (data == 0xffffffff) {
bar->trapped = true;
if (offset == pcrf->start)
bar->bar_sz = (bar->size & 0xffffffff);
else
bar->bar_sz = (bar->size >> 32);
return OPAL_SUCCESS;
}
/* Update BAR base address */
if (offset == pcrf->start) {
bar->base &= 0xffffffff00000000;
bar->base |= (data & 0xfffffff0);
} else {
bar->base &= 0x00000000ffffffff;
bar->base |= ((uint64_t)data << 32);
PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd);
npu_dev_bar_update(dev->npu->chip_id, bar,
!!(pci_cmd & PCI_CFG_CMD_MEM_EN));
}
/* We still depend on the normal path to update the
* cached config buffer.
*/
return OPAL_PARAMETER;
}
static int64_t npu_dev_cfg_bar(void *dev, struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t len, uint32_t *data,
bool write)
{
struct pci_virt_device *pvd = dev;
struct npu_dev *ndev = pvd->data;
if (write)
return npu_dev_cfg_bar_write(ndev, pcrf, offset, len, *data);
return npu_dev_cfg_bar_read(ndev, pcrf, offset, len, data);
}
static int64_t npu_dev_cfg_exp_devcap(void *dev,
struct pci_cfg_reg_filter *pcrf __unused,
uint32_t offset, uint32_t size,
uint32_t *data, bool write)
{
struct pci_virt_device *pvd = dev;
struct npu_dev *ndev = pvd->data;
assert(write);
if ((size != 2) || (offset & 1)) {
/* Short config writes are not supported */
prlog(PR_ERR, "NPU%d: Unsupported write to pcie control register\n",
ndev->phb->opal_id);
return OPAL_PARAMETER;
}
if (*data & PCICAP_EXP_DEVCTL_FUNC_RESET)
npu_dev_procedure_reset(ndev);
return OPAL_PARTIAL;
}
static struct npu_dev *bdfn_to_npu_dev(struct npu *p, uint32_t bdfn)
{
struct pci_virt_device *pvd;
/* Sanity check */
if (bdfn & ~0xff)
return NULL;
pvd = pci_virt_find_device(&p->phb, bdfn);
if (pvd)
return pvd->data;
return NULL;
}
#define NPU_CFG_READ(size, type) \
static int64_t npu_cfg_read##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type *data) \
{ \
uint32_t val; \
int64_t ret; \
\
ret = pci_virt_cfg_read(phb, bdfn, offset, sizeof(*data), &val); \
*data = (type)val; \
return ret; \
}
#define NPU_CFG_WRITE(size, type) \
static int64_t npu_cfg_write##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type data) \
{ \
uint32_t val = data; \
\
return pci_virt_cfg_write(phb, bdfn, offset, sizeof(data), val); \
}
NPU_CFG_READ(8, u8);
NPU_CFG_READ(16, u16);
NPU_CFG_READ(32, u32);
NPU_CFG_WRITE(8, u8);
NPU_CFG_WRITE(16, u16);
NPU_CFG_WRITE(32, u32);
static int __npu_dev_bind_pci_dev(struct phb *phb __unused,
struct pci_device *pd,
void *data)
{
struct npu_dev *dev = data;
struct dt_node *pci_dt_node;
char *pcislot;
/* Ignore non-nvidia PCI devices */
if ((pd->vdid & 0xffff) != 0x10de)
return 0;
/* Find the PCI device's slot location */
for (pci_dt_node = pd->dn;
pci_dt_node && !dt_find_property(pci_dt_node, "ibm,slot-label");
pci_dt_node = pci_dt_node->parent);
if (!pci_dt_node)
return 0;
pcislot = (char *)dt_prop_get(pci_dt_node, "ibm,slot-label");
prlog(PR_DEBUG, "NPU: comparing GPU %s and NPU %s\n",
pcislot, dev->slot_label);
if (streq(pcislot, dev->slot_label))
return 1;
return 0;
}
static void npu_dev_bind_pci_dev(struct npu_dev *dev)
{
struct phb *phb;
uint32_t i;
if (dev->pd)
return;
for (i = 0; i < 64; i++) {
if (dev->npu->phb.opal_id == i)
continue;
phb = pci_get_phb(i);
if (!phb)
continue;
dev->pd = pci_walk_dev(phb, NULL, __npu_dev_bind_pci_dev, dev);
if (dev->pd) {
dev->phb = phb;
/* Found the device, set the bit in config space */
PCI_VIRT_CFG_INIT_RO(dev->pvd, VENDOR_CAP_START +
VENDOR_CAP_PCI_DEV_OFFSET, 1, 0x01);
return;
}
}
prlog(PR_INFO, "%s: No PCI device for NPU device %04x:00:%02x.0 to bind to. If you expect a GPU to be there, this is a problem.\n",
__func__, dev->npu->phb.opal_id, dev->index);
}
static struct lock pci_npu_phandle_lock = LOCK_UNLOCKED;
/* Appends an NPU phandle to the given PCI device node ibm,npu
* property */
static void npu_append_pci_phandle(struct dt_node *dn, u32 phandle)
{
uint32_t *npu_phandles;
struct dt_property *pci_npu_phandle_prop;
size_t prop_len;
/* Use a lock to make sure no one else has a reference to an
* ibm,npu property (this assumes this is the only function
* that holds a reference to it). */
lock(&pci_npu_phandle_lock);
/* This function shouldn't be called unless ibm,npu exists */
pci_npu_phandle_prop = (struct dt_property *)
dt_require_property(dn, "ibm,npu", -1);
/* Need to append to the properties */
prop_len = pci_npu_phandle_prop->len;
prop_len += sizeof(*npu_phandles);
dt_resize_property(&pci_npu_phandle_prop, prop_len);
pci_npu_phandle_prop->len = prop_len;
npu_phandles = (uint32_t *) pci_npu_phandle_prop->prop;
npu_phandles[prop_len/sizeof(*npu_phandles) - 1] = phandle;
unlock(&pci_npu_phandle_lock);
}
static int npu_dn_fixup(struct phb *phb,
struct pci_device *pd,
void *data __unused)
{
struct npu *p = phb_to_npu(phb);
struct npu_dev *dev;
dev = bdfn_to_npu_dev(p, pd->bdfn);
assert(dev);
if (dev->phb || dev->pd)
return 0;
/* NPU devices require a slot location to associate with GPUs */
dev->slot_label = dt_prop_get(pd->dn, "ibm,slot-label");
/* Bind the emulated PCI device with the real one, which can't
* be done until the PCI devices are populated. Once the real
* PCI device is identified, we also need fix the device-tree
* for it
*/
npu_dev_bind_pci_dev(dev);
if (dev->phb && dev->pd && dev->pd->dn) {
if (dt_find_property(dev->pd->dn, "ibm,npu"))
npu_append_pci_phandle(dev->pd->dn, pd->dn->phandle);
else
dt_add_property_cells(dev->pd->dn, "ibm,npu", pd->dn->phandle);
dt_add_property_cells(pd->dn, "ibm,gpu", dev->pd->dn->phandle);
}
return 0;
}
static void npu_phb_final_fixup(struct phb *phb)
{
pci_walk_dev(phb, NULL, npu_dn_fixup, NULL);
}
static void npu_ioda_init(struct npu *p)
{
uint64_t *data64;
uint32_t i;
/* LXIVT - Disable all LSIs */
for (i = 0; i < ARRAY_SIZE(p->lxive_cache); i++) {
data64 = &p->lxive_cache[i];
*data64 = SETFIELD(NPU_IODA_LXIVT_PRIORITY, 0ul, 0xff);
*data64 = SETFIELD(NPU_IODA_LXIVT_SERVER, *data64, 0);
}
/* PCT - Reset to reserved PE# */
for (i = 0; i < ARRAY_SIZE(p->pce_cache); i++) {
data64 = &p->pce_cache[i];
*data64 = SETFIELD(NPU_IODA_PCT_PE, 0ul, 0ul);
*data64 |= NPU_IODA_PCT_LINK_ENABLED;
}
/* Clear TVT */
memset(p->tve_cache, 0, sizeof(p->tve_cache));
}
static int64_t npu_ioda_reset(struct phb *phb, bool purge)
{
struct npu *p = phb_to_npu(phb);
uint32_t i;
if (purge) {
NPUDBG(p, "Purging all IODA tables...\n");
npu_ioda_init(p);
}
/* LIST */
npu_ioda_sel(p, NPU_IODA_TBL_LIST, 0, true);
for (i = 0; i < 8; i++)
out_be64(p->at_regs + NPU_IODA_DATA0, 0x1);
/* LIXVT */
npu_ioda_sel(p, NPU_IODA_TBL_LXIVT, 0, true);
for (i = 0; i < ARRAY_SIZE(p->lxive_cache); i++)
out_be64(p->at_regs + NPU_IODA_DATA0, p->lxive_cache[i]);
/* PCT */
npu_ioda_sel(p, NPU_IODA_TBL_PCT, 0, true);
for (i = 0; i < ARRAY_SIZE(p->pce_cache); i++)
out_be64(p->at_regs + NPU_IODA_DATA0, p->pce_cache[i]);
/* TVT */
npu_ioda_sel(p, NPU_IODA_TBL_TVT, 0, true);
for (i = 0; i < ARRAY_SIZE(p->tve_cache); i++)
out_be64(p->at_regs + NPU_IODA_DATA0, p->tve_cache[i]);
return OPAL_SUCCESS;
}
static int npu_isn_valid(struct npu *p, uint32_t isn)
{
if (p->chip_id != p8_irq_to_chip(isn) || p->index != 0 ||
NPU_IRQ_NUM(isn) < NPU_LSI_IRQ_MIN ||
NPU_IRQ_NUM(isn) > NPU_LSI_IRQ_MAX) {
/**
* @fwts-label NPUisnInvalid
* @fwts-advice NVLink not functional
*/
prlog(PR_ERR, "NPU%d: isn 0x%x not valid for this NPU\n",
p->phb.opal_id, isn);
return false;
}
return true;
}
static int64_t npu_lsi_get_xive(struct irq_source *is, uint32_t isn,
uint16_t *server, uint8_t *prio)
{
struct npu *p = is->data;
uint32_t irq = NPU_IRQ_NUM(isn);
uint64_t lxive;
if (!npu_isn_valid(p, isn))
return OPAL_PARAMETER;
/* The content is fetched from the cache, which requires
* that the initial cache should be initialized with the
* default values
*/
irq -= NPU_LSI_IRQ_MIN;
lxive = p->lxive_cache[irq];
*server = GETFIELD(NPU_IODA_LXIVT_SERVER, lxive);
*prio = GETFIELD(NPU_IODA_LXIVT_PRIORITY, lxive);
return OPAL_SUCCESS;
}
static int64_t npu_lsi_set_xive(struct irq_source *is, uint32_t isn,
uint16_t server, uint8_t prio)
{
struct npu *p = is->data;
uint32_t irq = NPU_IRQ_NUM(isn);
uint64_t lxive;
if (!npu_isn_valid(p, isn))
return OPAL_PARAMETER;
/* Figure out LXIVT entry */
lxive = SETFIELD(NPU_IODA_LXIVT_SERVER, 0ul, server);
lxive = SETFIELD(NPU_IODA_LXIVT_PRIORITY, lxive, prio);
/* Cache LXIVT entry */
irq -= NPU_LSI_IRQ_MIN;
p->lxive_cache[irq] = lxive;
/* Update to LXIVT entry */
npu_ioda_sel(p, NPU_IODA_TBL_LXIVT, irq, false);
lxive = in_be64(p->at_regs + NPU_IODA_DATA0);
lxive = SETFIELD(NPU_IODA_LXIVT_SERVER, lxive, server);
lxive = SETFIELD(NPU_IODA_LXIVT_PRIORITY, lxive, prio);
out_be64(p->at_regs + NPU_IODA_DATA0, lxive);
return OPAL_SUCCESS;
}
static void npu_err_interrupt(struct irq_source *is, uint32_t isn)
{
struct npu *p = is->data;
uint32_t irq = NPU_IRQ_NUM(isn);
if (!npu_isn_valid(p, isn))
return;
/* There're 4 LSIs used for error reporting: 4/5 for data
* link error reporting while 6/7 for frozen PE detection
*/
irq -= NPU_LSI_IRQ_MIN;
switch (irq) {
case 4 ... 5:
prerror("Invalid NPU error interrupt received\n");
break;
case 6 ... 7:
opal_update_pending_evt(OPAL_EVENT_PCI_ERROR,
OPAL_EVENT_PCI_ERROR);
}
}
static uint64_t npu_lsi_attributes(struct irq_source *is, uint32_t isn)
{
struct npu *p = is->data;
uint32_t idx = isn - p->base_lsi;
if (idx >= 4)
return IRQ_ATTR_TARGET_OPAL | IRQ_ATTR_TARGET_RARE;
return IRQ_ATTR_TARGET_LINUX;
}
/* Error LSIs (skiboot owned) */
static const struct irq_source_ops npu_lsi_irq_ops = {
.get_xive = npu_lsi_get_xive,
.set_xive = npu_lsi_set_xive,
.attributes = npu_lsi_attributes,
.interrupt = npu_err_interrupt,
};
static void npu_register_irq(struct npu *p)
{
register_irq_source(&npu_lsi_irq_ops, p, p->base_lsi, 8);
}
static void npu_hw_init(struct npu *p)
{
/* 3 MMIO setup for AT */
out_be64(p->at_regs + NPU_LSI_SOURCE_ID,
SETFIELD(NPU_LSI_SRC_ID_BASE, 0ul, NPU_LSI_IRQ_MIN >> 4));
BUILD_ASSERT((NPU_LSI_IRQ_MIN & 0x07F0) == NPU_LSI_IRQ_MIN);
out_be64(p->at_regs + NPU_INTREP_TIMER, 0x0ul);
npu_ioda_reset(&p->phb, false);
}
static int64_t npu_map_pe_dma_window_real(struct phb *phb,
uint64_t pe_number,
uint16_t window_id,
uint64_t pci_start_addr,
uint64_t pci_mem_size)
{
struct npu *p = phb_to_npu(phb);
uint64_t end;
uint64_t tve;
/* Sanity check. Each PE has one corresponding TVE */
if (pe_number >= NPU_NUM_OF_PES ||
window_id != pe_number)
return OPAL_PARAMETER;
if (pci_mem_size) {
/* Enable */
end = pci_start_addr + pci_mem_size;
/* We have to be 16M aligned */
if ((pci_start_addr & 0x00ffffff) ||
(pci_mem_size & 0x00ffffff))
return OPAL_PARAMETER;
/*
* It *looks* like this is the max we can support (we need
* to verify this. Also we are not checking for rollover,
* but then we aren't trying too hard to protect ourselves
* againt a completely broken OS.
*/
if (end > 0x0003ffffffffffffull)
return OPAL_PARAMETER;
/*
* Put start address bits 49:24 into TVE[52:53]||[0:23]
* and end address bits 49:24 into TVE[54:55]||[24:47]
* and set TVE[51]
*/
tve = (pci_start_addr << 16) & (0xffffffull << 48);
tve |= (pci_start_addr >> 38) & (3ull << 10);
tve |= (end >> 8) & (0xfffffful << 16);
tve |= (end >> 40) & (3ull << 8);
tve |= PPC_BIT(51);
} else {
/* Disable */
tve = 0;
}
npu_ioda_sel(p, NPU_IODA_TBL_TVT, window_id, false);
out_be64(p->at_regs + NPU_IODA_DATA0, tve);
p->tve_cache[window_id] = tve;
return OPAL_SUCCESS;
}
static int64_t npu_map_pe_dma_window(struct phb *phb,
uint64_t pe_number,
uint16_t window_id,
uint16_t tce_levels,
uint64_t tce_table_addr,
uint64_t tce_table_size,
uint64_t tce_page_size)
{
struct npu *p = phb_to_npu(phb);
uint64_t tts_encoded;
uint64_t data64 = 0;
/* Sanity check. Each PE has one corresponding TVE */
if (pe_number >= NPU_NUM_OF_PES ||
window_id != pe_number)
return OPAL_PARAMETER;
/* Special condition, zero TCE table size used to disable
* the TVE.
*/
if (!tce_table_size) {
npu_ioda_sel(p, NPU_IODA_TBL_TVT, window_id, false);
out_be64(p->at_regs + NPU_IODA_DATA0, 0ul);
p->tve_cache[window_id] = 0ul;
return OPAL_SUCCESS;
}
/* Additional arguments validation */
if (tce_levels < 1 ||
tce_levels > 4 ||
!is_pow2(tce_table_size) ||
tce_table_size < 0x1000)
return OPAL_PARAMETER;
/* TCE table size */
data64 = SETFIELD(NPU_IODA_TVT_TTA, 0ul, tce_table_addr >> 12);
tts_encoded = ilog2(tce_table_size) - 11;
if (tts_encoded > 39)
return OPAL_PARAMETER;
data64 = SETFIELD(NPU_IODA_TVT_SIZE, data64, tts_encoded);
/* TCE page size */
switch (tce_page_size) {
case 0x10000: /* 64K */
data64 = SETFIELD(NPU_IODA_TVT_PSIZE, data64, 5);
break;
case 0x1000000: /* 16M */
data64 = SETFIELD(NPU_IODA_TVT_PSIZE, data64, 13);
break;
case 0x10000000: /* 256M */
data64 = SETFIELD(NPU_IODA_TVT_PSIZE, data64, 17);
break;
case 0x1000: /* 4K */
default:
data64 = SETFIELD(NPU_IODA_TVT_PSIZE, data64, 1);
}
/* Number of levels */
data64 = SETFIELD(NPU_IODA_TVT_LEVELS, data64, tce_levels - 1);
/* Update to hardware */
npu_ioda_sel(p, NPU_IODA_TBL_TVT, window_id, false);
out_be64(p->at_regs + NPU_IODA_DATA0, data64);
p->tve_cache[window_id] = data64;
return OPAL_SUCCESS;
}
static int64_t npu_set_pe(struct phb *phb,
uint64_t pe_number,
uint64_t bdfn,
uint8_t bcompare,
uint8_t dcompare,
uint8_t fcompare,
uint8_t action)
{
struct npu *p = phb_to_npu(phb);
struct npu_dev *dev;
uint32_t link_idx;
uint64_t *data64;
/* Sanity check */
if (action != OPAL_MAP_PE &&
action != OPAL_UNMAP_PE)
return OPAL_PARAMETER;
if (pe_number >= NPU_NUM_OF_PES)
return OPAL_PARAMETER;
/* All emulated PCI devices hooked to root bus, whose
* bus number is zero.
*/
dev = bdfn_to_npu_dev(p, bdfn);
if ((bdfn >> 8) || !dev)
return OPAL_PARAMETER;
link_idx = dev->index;
dev->pe_number = pe_number;
/* Separate links will be mapped to different PEs */
if (bcompare != OpalPciBusAll ||
dcompare != OPAL_COMPARE_RID_DEVICE_NUMBER ||
fcompare != OPAL_COMPARE_RID_FUNCTION_NUMBER)
return OPAL_UNSUPPORTED;
/* Map the link to the corresponding PE */
data64 = &p->pce_cache[link_idx];
if (action == OPAL_MAP_PE)
*data64 = SETFIELD(NPU_IODA_PCT_PE, *data64,
pe_number);
else
*data64 = SETFIELD(NPU_IODA_PCT_PE, *data64,
NPU_NUM_OF_PES);
*data64 |= NPU_IODA_PCT_LINK_ENABLED;
npu_ioda_sel(p, NPU_IODA_TBL_PCT, link_idx, false);
out_be64(p->at_regs + NPU_IODA_DATA0, *data64);
return OPAL_SUCCESS;
}
static int64_t npu_get_link_state(struct pci_slot *slot __unused, uint8_t *val)
{
/* As we're emulating all PCI stuff, the link bandwidth
* isn't big deal anyway.
*/
*val = OPAL_SHPC_LINK_UP_x1;
return OPAL_SUCCESS;
}
static int64_t npu_get_power_state(struct pci_slot *slot __unused, uint8_t *val)
{
*val = PCI_SLOT_POWER_ON;
return OPAL_SUCCESS;
}
static int64_t npu_hreset(struct pci_slot *slot __unused)
{
prlog(PR_DEBUG, "NPU: driver should call reset procedure here\n");
return OPAL_SUCCESS;
}
static int64_t npu_freset(struct pci_slot *slot __unused)
{
/* FIXME: PHB fundamental reset, which need to be
* figured out later. It's used by EEH recovery
* upon fenced AT.
*/
return OPAL_SUCCESS;
}
static struct pci_slot *npu_slot_create(struct phb *phb)
{
struct pci_slot *slot;
slot = pci_slot_alloc(phb, NULL);
if (!slot)
return slot;
/* Elementary functions */
slot->ops.get_presence_state = NULL;
slot->ops.get_link_state = npu_get_link_state;
slot->ops.get_power_state = npu_get_power_state;
slot->ops.get_attention_state = NULL;
slot->ops.get_latch_state = NULL;
slot->ops.set_power_state = NULL;
slot->ops.set_attention_state = NULL;
slot->ops.prepare_link_change = NULL;
slot->ops.poll_link = NULL;
slot->ops.hreset = npu_hreset;
slot->ops.freset = npu_freset;
slot->ops.creset = NULL;
return slot;
}
static int64_t npu_freeze_status(struct phb *phb,
uint64_t pe_number __unused,
uint8_t *freeze_state,
uint16_t *pci_error_type __unused,
uint16_t *severity __unused,
uint64_t *phb_status __unused)
{
/* FIXME: When it's called by skiboot PCI config accessor,
* the PE number is fixed to 0, which is incorrect. We need
* introduce another PHB callback to translate it. For now,
* it keeps the skiboot PCI enumeration going.
*/
struct npu *p = phb_to_npu(phb);
if (p->fenced)
*freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
else
*freeze_state = OPAL_EEH_STOPPED_NOT_FROZEN;
return OPAL_SUCCESS;
}
static int64_t npu_eeh_next_error(struct phb *phb,
uint64_t *first_frozen_pe,
uint16_t *pci_error_type,
uint16_t *severity)
{
struct npu *p = phb_to_npu(phb);
int i;
uint64_t result = 0;
*first_frozen_pe = -1;
*pci_error_type = OPAL_EEH_NO_ERROR;
*severity = OPAL_EEH_SEV_NO_ERROR;
if (p->fenced) {
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_PHB_FENCED;
return OPAL_SUCCESS;
}
npu_ioda_sel(p, NPU_IODA_TBL_PESTB, 0, true);
for (i = 0; i < NPU_NUM_OF_PES; i++) {
result = in_be64(p->at_regs + NPU_IODA_DATA0);
if (result > 0) {
*first_frozen_pe = i;
*pci_error_type = OPAL_EEH_PE_ERROR;
*severity = OPAL_EEH_SEV_PE_ER;
break;
}
}
return OPAL_SUCCESS;
}
/* For use in error injection and handling. */
void npu_set_fence_state(struct npu *p, bool fence) {
p->fenced = fence;
if (fence)
prlog(PR_ERR, "NPU: Chip %x is fenced, reboot required.\n",
p->chip_id);
else
prlog(PR_WARNING, "NPU: un-fencing is dangerous and should \
only be used for development purposes.");
}
/* Sets the NPU to trigger an error when a DMA occurs */
static int64_t npu_err_inject(struct phb *phb, uint64_t pe_number,
uint32_t type, uint32_t func __unused,
uint64_t addr __unused, uint64_t mask __unused)
{
struct npu *p = phb_to_npu(phb);
struct npu_dev *dev = NULL;
int i;
if (pe_number >= NPU_NUM_OF_PES) {
prlog(PR_ERR, "NPU: error injection failed, bad PE given\n");
return OPAL_PARAMETER;
}
for (i = 0; i < p->total_devices; i++) {
if (p->devices[i].pe_number == pe_number) {
dev = &p->devices[i];
break;
}
}
if (!dev) {
prlog(PR_ERR, "NPU: couldn't find device with PE%llx\n", pe_number);
return OPAL_PARAMETER;
}
/* TODO: extend this to conform to OPAL injection standards */
if (type > 1) {
prlog(PR_ERR, "NPU: invalid error injection type\n");
return OPAL_PARAMETER;
} else if (type == 1) {
/* Emulate fence mode. */
npu_set_fence_state(p, true);
} else {
/* Cause a freeze with an invalid MMIO read. If the BAR is not
* enabled, this will checkstop the machine.
*/
npu_dev_bar_update(p->chip_id, &dev->bar, true);
in_be64((void *)dev->bar.base);
}
return OPAL_SUCCESS;
}
static const struct phb_ops npu_ops = {
.cfg_read8 = npu_cfg_read8,
.cfg_read16 = npu_cfg_read16,
.cfg_read32 = npu_cfg_read32,
.cfg_write8 = npu_cfg_write8,
.cfg_write16 = npu_cfg_write16,
.cfg_write32 = npu_cfg_write32,
.choose_bus = NULL,
.get_reserved_pe_number = NULL,
.device_init = NULL,
.phb_final_fixup = npu_phb_final_fixup,
.ioda_reset = npu_ioda_reset,