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npu2.c
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npu2.c
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/* Copyright 2013-2016 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <skiboot.h>
#include <io.h>
#include <timebase.h>
#include <pci-cfg.h>
#include <pci.h>
#include <pci-slot.h>
#include <pci-virt.h>
#include <interrupts.h>
#include <opal.h>
#include <opal-api.h>
#include <cpu.h>
#include <device.h>
#include <ccan/str/str.h>
#include <ccan/array_size/array_size.h>
#include <affinity.h>
#include <npu2-regs.h>
#include <npu2.h>
#include <lock.h>
#include <xscom.h>
#include <bitutils.h>
#include <chip.h>
#include <phys-map.h>
#include <nvram.h>
#include <xive.h>
#define NPU2_IRQ_BASE_SHIFT 13
#define NPU2_N_DL_IRQS 23
#define NPU2_N_DL_IRQS_ALIGN 32
#define VENDOR_CAP_START 0x80
#define VENDOR_CAP_END 0x90
#define VENDOR_CAP_LEN 0x10
#define VENDOR_CAP_VERSION 0x01
#define VENDOR_CAP_PCI_DEV_OFFSET 0x0d
/*
* NPU2 BAR layout definition. We have 3 stacks and each of them
* contains 2 bricks. So every NPU2 has 6 bricks in total. There are 2
* PHY BARs and each of them is shared by 3 bricks. Every brick has
* one NTL BAR and two bricks share one GENID BAR. There is also a
* global MMIO BAR. We only expose DL and GENID BARs to the OS and all
* other BARs will be hidden in skiboot.
*
* Before the global MMIO BAR is configured, scom is the only way to
* access the BAR registers. At NPU2 PHB probing time, we rely on scom
* to assign all BARs until the global MMIO BAR is established.
*
* We need to access 4 SM registers in the same stack in order to
* configure one particular BAR.
*/
static bool is_p9dd1(void)
{
struct proc_chip *chip = next_chip(NULL);
return chip &&
(chip->type == PROC_CHIP_P9_NIMBUS ||
chip->type == PROC_CHIP_P9_CUMULUS) &&
(chip->ec_level & 0xf0) == 0x10;
}
/*
* We use the indirect method because it uses the same addresses as
* the MMIO offsets (NPU RING)
*/
static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base,
uint64_t addr, uint64_t size)
{
uint64_t isa = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_ADDR :
NPU2_MISC_SCOM_IND_SCOM_ADDR;
addr = SETFIELD(NPU2_MISC_DA_ADDR, 0ull, addr);
addr = SETFIELD(NPU2_MISC_DA_LEN, addr, size);
xscom_write(gcid, scom_base + isa, addr);
}
static void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
uint64_t reg, uint64_t size,
uint64_t val)
{
uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA :
NPU2_MISC_SCOM_IND_SCOM_DATA;
npu2_scom_set_addr(gcid, scom_base, reg, size);
xscom_write(gcid, scom_base + isd, val);
}
static uint64_t npu2_scom_read(uint64_t gcid, uint64_t scom_base,
uint64_t reg, uint64_t size)
{
uint64_t val;
uint64_t isd = is_p9dd1() ? NPU2_DD1_MISC_SCOM_IND_SCOM_DATA :
NPU2_MISC_SCOM_IND_SCOM_DATA;
npu2_scom_set_addr(gcid, scom_base, reg, size);
xscom_read(gcid, scom_base + isd, &val);
return val;
}
void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val)
{
npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_4B,
(uint64_t)val << 32);
}
uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg)
{
return npu2_scom_read(p->chip_id, p->xscom_base, reg,
NPU2_MISC_DA_LEN_4B) >> 32;
}
void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val)
{
npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, val);
}
uint64_t npu2_read(struct npu2 *p, uint64_t reg)
{
return npu2_scom_read(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B);
}
void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask)
{
uint64_t new_val;
new_val = npu2_read(p, reg);
new_val &= ~mask;
new_val |= val & mask;
npu2_scom_write(p->chip_id, p->xscom_base, reg, NPU2_MISC_DA_LEN_8B, new_val);
}
/* Set a specific flag in the vendor config space */
void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag)
{
ndev->link_flags |= flag;
PCI_VIRT_CFG_INIT_RO(ndev->pvd, VENDOR_CAP_START +
VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->link_flags);
}
void npu2_clear_link_flag(struct npu2_dev *ndev, uint8_t flag)
{
ndev->link_flags &= ~flag;
PCI_VIRT_CFG_INIT_RO(ndev->pvd, VENDOR_CAP_START +
VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->link_flags);
}
static inline void npu2_ioda_sel(struct npu2 *p, uint32_t table,
uint32_t index, bool autoinc)
{
out_be64(p->regs + NPU2_ATS_IODA_TBL,
(autoinc ? NPU2_ATS_IODA_TBL_AUTOINC : 0ul) |
SETFIELD(NPU2_ATS_IODA_TBL_SELECT, 0ul, table) |
SETFIELD(NPU2_ATS_IODA_TBL_INDEX, 0ul, index));
}
static struct npu2_dev *npu2_bdf_to_dev(struct npu2 *p,
uint32_t bdfn)
{
struct pci_virt_device *pvd;
/* All emulated devices are attached to root bus */
if (bdfn & ~0xff)
return NULL;
pvd = pci_virt_find_device(&p->phb, bdfn);
if (pvd)
return pvd->data;
return NULL;
}
static inline void npu2_get_bar(uint32_t gcid, struct npu2_bar *bar)
{
phys_map_get(gcid, bar->type, bar->index, &bar->base, &bar->size);
}
static void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar)
{
uint64_t reg, val;
int enabled;
reg = NPU2_REG_OFFSET(0, NPU2_BLOCK_SM_0, bar->reg);
val = npu2_read(p, reg);
switch (NPU2_REG(bar->reg)) {
case NPU2_PHY_BAR:
bar->base = GETFIELD(NPU2_PHY_BAR_ADDR, val) << 21;
enabled = GETFIELD(NPU2_PHY_BAR_ENABLE, val);
if (NPU2_REG_STACK(reg) == NPU2_STACK_STCK_2)
/* This is the global MMIO BAR */
bar->size = 0x1000000;
else
bar->size = 0x200000;
break;
case NPU2_NTL0_BAR:
case NPU2_NTL1_BAR:
bar->base = GETFIELD(NPU2_NTL_BAR_ADDR, val) << 16;
enabled = GETFIELD(NPU2_NTL_BAR_ENABLE, val);
if (is_p9dd1())
bar->size = 0x20000;
else
bar->size = 0x10000 << GETFIELD(NPU2_NTL_BAR_SIZE, val);
break;
case NPU2_GENID_BAR:
bar->base = GETFIELD(NPU2_GENID_BAR_ADDR, val) << 16;
enabled = GETFIELD(NPU2_GENID_BAR_ENABLE, val);
bar->size = 0x20000;
break;
default:
bar->base = 0ul;
enabled = 0;
bar->size = 0;
break;
}
bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED, bar->flags, enabled);
}
static void npu2_write_bar(struct npu2 *p,
struct npu2_bar *bar,
uint32_t gcid,
uint32_t scom)
{
uint64_t reg, val, enable = !!(bar->flags & NPU2_BAR_FLAG_ENABLED);
int block;
switch (NPU2_REG(bar->reg)) {
case NPU2_PHY_BAR:
val = SETFIELD(NPU2_PHY_BAR_ADDR, 0ul, bar->base >> 21);
val = SETFIELD(NPU2_PHY_BAR_ENABLE, val, enable);
break;
case NPU2_NTL0_BAR:
case NPU2_NTL1_BAR:
val = SETFIELD(NPU2_NTL_BAR_ADDR, 0ul, bar->base >> 16);
val = SETFIELD(NPU2_NTL_BAR_ENABLE, val, enable);
if (!is_p9dd1())
val = SETFIELD(NPU2_NTL_BAR_SIZE, val, 1);
break;
case NPU2_GENID_BAR:
val = SETFIELD(NPU2_GENID_BAR_ADDR, 0ul, bar->base >> 16);
val = SETFIELD(NPU2_GENID_BAR_ENABLE, val, enable);
break;
default:
val = 0ul;
}
for (block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; block++) {
reg = NPU2_REG_OFFSET(0, block, bar->reg);
if (p)
npu2_write(p, reg, val);
else
npu2_scom_write(gcid, scom, reg, NPU2_MISC_DA_LEN_8B, val);
}
}
/* Trap for PCI command (0x4) to enable or disable device's BARs */
static int64_t npu2_cfg_write_cmd(void *dev,
struct pci_cfg_reg_filter *pcrf __unused,
uint32_t offset, uint32_t size,
uint32_t *data, bool write)
{
struct pci_virt_device *pvd = dev;
struct npu2_dev *ndev = pvd->data;
struct npu2_bar *ntl_npu_bar, *genid_npu_bar;
bool enabled;
if (!write)
return OPAL_PARTIAL;
if (offset != PCI_CFG_CMD)
return OPAL_PARAMETER;
if (size != 1 && size != 2 && size != 4)
return OPAL_PARAMETER;
/*
* Enable or disable NTL and GENID BAR. Two bricks share
* one GENID BAR, which is exposed via the first brick.
*/
enabled = !!(*data & PCI_CFG_CMD_MEM_EN);
ntl_npu_bar = &ndev->bars[0].npu2_bar;
genid_npu_bar = &ndev->bars[1].npu2_bar;
ntl_npu_bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED, ntl_npu_bar->flags, enabled);
npu2_write_bar(ndev->npu, ntl_npu_bar, 0, 0);
/*
* Enable/disable the GENID BAR. Two bricks share one GENID
* BAR which is exposed via the first brick so we need to
* track the enables separately.
*/
if (NPU2DEV_BRICK(ndev))
genid_npu_bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED1, genid_npu_bar->flags,
enabled);
else
genid_npu_bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED0, genid_npu_bar->flags,
enabled);
/* Enable the BAR if either device requests it enabled, otherwise disable it */
genid_npu_bar->flags = SETFIELD(NPU2_BAR_FLAG_ENABLED, genid_npu_bar->flags,
!!(genid_npu_bar->flags & (NPU2_BAR_FLAG_ENABLED0 |
NPU2_BAR_FLAG_ENABLED1)));
npu2_write_bar(ndev->npu, genid_npu_bar, 0, 0);
return OPAL_PARTIAL;
}
static int64_t npu2_cfg_read_bar(struct npu2_dev *dev __unused,
struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t size,
uint32_t *data)
{
struct npu2_pcie_bar *bar = (struct npu2_pcie_bar *) pcrf->data;
if (!(bar->flags & NPU2_PCIE_BAR_FLAG_TRAPPED))
return OPAL_PARTIAL;
if ((size != 4) ||
(offset != pcrf->start && offset != pcrf->start + 4))
return OPAL_PARAMETER;
if (bar->flags & NPU2_PCIE_BAR_FLAG_SIZE_HI)
*data = bar->npu2_bar.size >> 32;
else
*data = bar->npu2_bar.size;
bar->flags &= ~(NPU2_PCIE_BAR_FLAG_TRAPPED | NPU2_PCIE_BAR_FLAG_SIZE_HI);
return OPAL_SUCCESS;
}
static int64_t npu2_cfg_write_bar(struct npu2_dev *dev,
struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t size,
uint32_t data)
{
struct pci_virt_device *pvd = dev->pvd;
struct npu2_pcie_bar *bar = (struct npu2_pcie_bar *) pcrf->data;
struct npu2_bar old_bar, *npu2_bar = &bar->npu2_bar;
uint32_t pci_cmd;
if ((size != 4) ||
(offset != pcrf->start && offset != pcrf->start + 4))
return OPAL_PARAMETER;
/* Return BAR size on next read */
if (data == 0xffffffff) {
bar->flags |= NPU2_PCIE_BAR_FLAG_TRAPPED;
if (offset == pcrf->start + 4)
bar->flags |= NPU2_PCIE_BAR_FLAG_SIZE_HI;
return OPAL_SUCCESS;
}
if (offset == pcrf->start) {
npu2_bar->base &= 0xffffffff00000000;
npu2_bar->base |= (data & 0xfffffff0);
} else {
npu2_bar->base &= 0x00000000ffffffff;
npu2_bar->base |= ((uint64_t)data << 32);
PCI_VIRT_CFG_NORMAL_RD(pvd, PCI_CFG_CMD, 4, &pci_cmd);
if (NPU2_REG(npu2_bar->reg) == NPU2_GENID_BAR && NPU2DEV_BRICK(dev))
npu2_bar->base -= 0x10000;
old_bar.reg = npu2_bar->reg;
npu2_read_bar(dev->npu, &old_bar);
/* Only allow changing the base address if the BAR is not enabled */
if ((npu2_bar->flags & NPU2_BAR_FLAG_ENABLED) &&
(npu2_bar->base != old_bar.base)) {
npu2_bar->base = old_bar.base;
return OPAL_HARDWARE;
}
npu2_write_bar(dev->npu, &bar->npu2_bar, 0, 0);
}
/* To update the config cache */
return OPAL_PARTIAL;
}
static int64_t npu2_dev_cfg_bar(void *dev, struct pci_cfg_reg_filter *pcrf,
uint32_t offset, uint32_t len, uint32_t *data,
bool write)
{
struct pci_virt_device *pvd = dev;
struct npu2_dev *ndev = (struct npu2_dev *) pvd->data;
if (write)
return npu2_cfg_write_bar(ndev, pcrf, offset, len, *data);
return npu2_cfg_read_bar(ndev, pcrf, offset, len, data);
}
static int64_t npu2_dev_cfg_exp_devcap(void *dev,
struct pci_cfg_reg_filter *pcrf __unused,
uint32_t offset, uint32_t size,
uint32_t *data, bool write)
{
struct pci_virt_device *pvd = dev;
struct npu2_dev *ndev = pvd->data;
assert(write);
if ((size != 2) || (offset & 1)) {
/* Short config writes are not supported */
prlog(PR_ERR, "NPU%d: Unsupported write to pcie control register\n",
ndev->phb->opal_id);
return OPAL_PARAMETER;
}
if (*data & PCICAP_EXP_DEVCTL_FUNC_RESET)
npu2_dev_procedure_reset(ndev);
return OPAL_PARTIAL;
}
#define NPU2_CFG_READ(size, type) \
static int64_t npu2_cfg_read##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type *data) \
{ \
uint32_t val; \
int64_t ret; \
\
ret = pci_virt_cfg_read(phb, bdfn, offset, \
sizeof(*data), &val); \
*data = (type)val; \
return ret; \
}
#define NPU2_CFG_WRITE(size, type) \
static int64_t npu2_cfg_write##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type data) \
{ \
uint32_t val = data; \
int64_t ret; \
\
ret = pci_virt_cfg_write(phb, bdfn, offset, \
sizeof(data), val); \
return ret; \
}
NPU2_CFG_READ(8, u8);
NPU2_CFG_READ(16, u16);
NPU2_CFG_READ(32, u32);
NPU2_CFG_WRITE(8, u8);
NPU2_CFG_WRITE(16, u16);
NPU2_CFG_WRITE(32, u32);
static int __npu2_dev_bind_pci_dev(struct phb *phb __unused,
struct pci_device *pd,
void *data)
{
struct npu2_dev *dev = data;
struct dt_node *pci_dt_node;
char *pcislot;
/* Ignore non-nvidia PCI devices */
if ((pd->vdid & 0xffff) != 0x10de)
return 0;
/* Find the PCI device's slot location */
for (pci_dt_node = pd->dn;
pci_dt_node && !dt_find_property(pci_dt_node, "ibm,slot-label");
pci_dt_node = pci_dt_node->parent);
if (!pci_dt_node)
return 0;
pcislot = (char *)dt_prop_get(pci_dt_node, "ibm,slot-label");
prlog(PR_DEBUG, "NPU2: comparing GPU '%s' and NPU2 '%s'\n",
pcislot, dev->slot_label);
if (streq(pcislot, dev->slot_label))
return 1;
return 0;
}
static void npu2_dev_bind_pci_dev(struct npu2_dev *dev)
{
struct phb *phb;
uint32_t i;
if (dev->pd)
return;
for (i = 0; i < 64; i++) {
if (dev->npu->phb.opal_id == i)
continue;
phb = pci_get_phb(i);
if (!phb)
continue;
dev->pd = pci_walk_dev(phb, NULL, __npu2_dev_bind_pci_dev, dev);
if (dev->pd) {
dev->phb = phb;
/* Found the device, set the bit in config space */
npu2_set_link_flag(dev, NPU2_DEV_PCI_LINKED);
return;
}
}
prlog(PR_INFO, "%s: No PCI device for NPU2 device %04x:00:%02x.0 to bind to. If you expect a GPU to be there, this is a problem.\n",
__func__, dev->npu->phb.opal_id, dev->index);
}
static struct lock pci_npu_phandle_lock = LOCK_UNLOCKED;
static void npu2_append_phandle(struct dt_node *dn,
u32 phandle)
{
struct dt_property *prop;
uint32_t *npu_phandles;
size_t len;
/*
* Use a lock to make sure no one else has a reference to an
* ibm,npu property (this assumes this is the only function
* that holds a reference to it)
*/
lock(&pci_npu_phandle_lock);
/* This function shouldn't be called unless ibm,npu exists */
prop = (struct dt_property *)dt_require_property(dn, "ibm,npu", -1);
/* Need to append to the properties */
len = prop->len + sizeof(*npu_phandles);
dt_resize_property(&prop, len);
prop->len = len;
npu_phandles = (uint32_t *)prop->prop;
npu_phandles[len / sizeof(*npu_phandles) - 1] = phandle;
unlock(&pci_npu_phandle_lock);
}
static struct dt_node *npu2_create_memory_dn(uint64_t addr, uint64_t size)
{
struct dt_node *mem;
char *name;
size_t namesz;
static u32 chip_id = 255;
/*
* Find and return the node if it already exists.
*/
namesz = sizeof("memory@") + STR_MAX_CHARS(addr);
name = malloc(namesz);
if (!name)
return NULL;
snprintf(name, namesz, "memory@%llx", (long long)addr);
mem = dt_find_by_name(dt_root, name);
free(name);
if (mem)
return mem;
mem = dt_new_addr(dt_root, "memory", addr);
if (!mem)
return NULL;
dt_add_property_string(mem, "device_type", "memory");
dt_add_property_string(mem, "compatible", "ibm,coherent-device-memory");
dt_add_property_u64s(mem, "reg", addr, size);
dt_add_property_cells(mem, "ibm,chip-id", chip_id);
dt_add_property_u64s(mem, "linux,usable-memory", addr, 0);
dt_add_property_cells(mem, "ibm,associativity", 4, chip_id, chip_id, chip_id, chip_id);
chip_id--;
assert(chip_id);
return mem;
}
/* There are potentially multiple links per GPU, so lookup the GPU memory based
* on bdfn. */
static void npu2_get_gpu_base(struct npu2_dev *ndev, uint64_t *addr, uint64_t *size)
{
int group;
group = (ndev->bdfn >> 3) & 0x1f;
phys_map_get(ndev->npu->chip_id, GPU_MEM, group, addr, size);
}
static void npu2_dn_fixup_gmb(struct dt_node *pd_dn, struct npu2_dev *ndev)
{
uint64_t gpu_base, gpu_size, gta;
struct dt_node *mem_dn;
npu2_get_gpu_base(ndev, &gpu_base, &gpu_size);
mem_dn = npu2_create_memory_dn(gpu_base, gpu_size);
assert(mem_dn);
dt_add_property_cells(pd_dn, "memory-region", mem_dn->phandle);
/* Coral mode address compression. This is documented in Figure 3.5
* "P9->GPU RA Compression (Coral) of the NPU2 workbook". */
gta = ((gpu_base >> 42) & 0x1) << 42;
gta |= ((gpu_base >> 45) & 0x3) << 43;
gta |= ((gpu_base >> 49) & 0x3) << 45;
gta |= gpu_base & ((1UL << 43) - 1);
dt_add_property_u64s(pd_dn, "ibm,device-tgt-addr", gta);
}
static int npu2_assign_gmb(struct npu2_dev *ndev)
{
struct npu2 *p = ndev->npu;
int peers, mode;
uint32_t bdfn;
uint64_t base, size, reg, val, old_val, gmb;
/* Need to work out number of link peers. This amount to
* working out the maximum function number. So work start at
* the highest bdfn (fn = 6) and count back until we find a
* npu2_dev. */
for (bdfn = (ndev->bdfn & ~0x7) | NPU2_LINKS_PER_CHIP;
(bdfn & 0x7) != 0x7; bdfn = (bdfn & ~0x7) | ((bdfn & 0x7) - 1))
if (npu2_bdf_to_dev(p, bdfn))
break;
peers = bdfn & 0x7;
npu2_get_gpu_base(ndev, &base, &size);
/* Base address is in GB */
base >>= 30;
val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, 0ULL, 4);
val = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, val, base);
val = SETFIELD(NPU2_MEM_BAR_GROUP | NPU2_MEM_BAR_CHIP, val, p->chip_id);
val = SETFIELD(NPU2_MEM_BAR_POISON, val, 1);
val = SETFIELD(NPU2_MEM_BAR_GRANULE, val, 0);
/* We don't know how much memory the GPU has, so we may as well just
* pass the whole aperture through at this point. */
val = SETFIELD(NPU2_MEM_BAR_BAR_SIZE, val, ilog2(size >> 30));
switch (peers) {
case 0:
mode = 0;
break;
case 1:
mode = 1;
break;
case 2:
mode = 3;
break;
case 3:
mode = 6;
break;
case 5:
mode = 10;
break;
default:
/* Hardware does not support this configuration */
assert(0);
}
mode += ndev->bdfn & 0x7;
val = SETFIELD(NPU2_MEM_BAR_MODE, val, mode);
gmb = NPU2_GPU0_MEM_BAR;
if (NPU2DEV_BRICK(ndev) && !is_p9dd1())
gmb = NPU2_GPU1_MEM_BAR;
reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev),
NPU2_BLOCK_SM_0, gmb);
if (is_p9dd1()) {
old_val = npu2_read(p, reg);
if (NPU2DEV_BRICK(ndev))
val = SETFIELD(PPC_BITMASK(32, 63), old_val, val >> 32);
else
val = SETFIELD(PPC_BITMASK(0, 31), old_val, val >> 32);
}
npu2_write(p, reg, val);
reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev),
NPU2_BLOCK_SM_1, gmb);
npu2_write(p, reg, val);
reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev),
NPU2_BLOCK_SM_2, gmb);
npu2_write(p, reg, val);
reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev),
NPU2_BLOCK_SM_3, gmb);
npu2_write(p, reg, val);
return 0;
}
static int npu2_dn_fixup(struct phb *phb,
struct pci_device *pd,
void *data __unused)
{
struct npu2 *p = phb_to_npu2(phb);
struct npu2_dev *dev;
uint32_t speed;
dev = npu2_bdf_to_dev(p, pd->bdfn);
assert(dev);
if (dev->phb || dev->pd)
return 0;
npu2_assign_gmb(dev);
npu2_dn_fixup_gmb(pd->dn, dev);
dt_add_property_cells(pd->dn, "ibm,nvlink", dev->dt_node->phandle);
/*
* NVLink supports multiple speeds and device drivers need to know what
* speed has been set by firmware. Hostboot does the inits that set the
* link speed and tell us via HDAT and we need to copy that from the
* link node.
*/
speed = dt_prop_get_u32_def(dev->dt_node, "nvidia,link-speed", 0xff);
if (speed != 0xff)
dt_add_property_cells(pd->dn, "ibm,nvlink-speed", speed);
/* NPU2 devices require a slot location to associate with GPUs */
dev->slot_label = dt_prop_get_def(pd->dn, "ibm,slot-label", NULL);
if (!dev->slot_label) {
/**
* @fwts-label NPUNoPHBSlotLabel
* @fwts-advice No GPU/NPU2 slot information was found.
* NVLink2 functionality will not work.
*/
prlog(PR_ERR, "NPU2: Cannot find GPU slot information\n");
return 0;
}
/*
* Bind the emulated PCI device with the real one, which can't
* be done until the PCI devices are populated. Once the real
* PCI device is identified, we also need fix the device-tree
* for it
*/
npu2_dev_bind_pci_dev(dev);
if (dev->phb && dev->pd && dev->pd->dn) {
if (dt_find_property(dev->pd->dn, "ibm,npu"))
npu2_append_phandle(dev->pd->dn, pd->dn->phandle);
else
dt_add_property_cells(dev->pd->dn, "ibm,npu", pd->dn->phandle);
dt_add_property_cells(pd->dn, "ibm,gpu", dev->pd->dn->phandle);
dev->gpu_bdfn = dev->pd->bdfn;
}
return 0;
}
static void npu2_phb_final_fixup(struct phb *phb)
{
pci_walk_dev(phb, NULL, npu2_dn_fixup, NULL);
}
static void npu2_init_ioda_cache(struct npu2 *p)
{
uint64_t val[2];
uint32_t i;
/*
* PE mapping: there are two sets of registers. One of them
* is used to map PEs for transactions. Another set is used
* for error routing. We should have consistent setting in
* both of them. Note that each brick can support 3 PEs at
* the maximal degree. For now, we just support one PE per
* brick.
*/
val[0] = NPU2_CQ_BRICK_BDF2PE_MAP_ENABLE;
val[0] = SETFIELD(NPU2_CQ_BRICK_BDF2PE_MAP_PE,
val[0], NPU2_RESERVED_PE_NUM);
val[1] = NPU2_MISC_BRICK_BDF2PE_MAP_ENABLE;
val[1] = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_PE,
val[1], NPU2_RESERVED_PE_NUM);
for (i = 0; i < ARRAY_SIZE(p->bdf2pe_cache); i++) {
if (i < ARRAY_SIZE(p->bdf2pe_cache))
p->bdf2pe_cache[i] = SETFIELD(NPU2_CQ_BRICK_BDF2PE_MAP_BDF,
val[0], i / 3);
else
p->bdf2pe_cache[i] = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_BDF,
val[1], i / 3);
if (i % 3)
p->bdf2pe_cache[i] = 0ul;
}
/* TVT */
memset(p->tve_cache, 0, sizeof(p->tve_cache));
}
static int64_t npu2_ioda_reset(struct phb *phb, bool purge)
{
struct npu2 *p = phb_to_npu2(phb);
uint32_t i;
if (purge) {
NPU2DBG(p, "Purging all IODA tables...\n");
npu2_init_ioda_cache(p);
}
/* TVT */
npu2_ioda_sel(p, NPU2_ATS_IODA_TBL_TVT, 0, true);
for (i = 0; i < ARRAY_SIZE(p->tve_cache); i++)
out_be64(p->regs + NPU2_ATS_IODA_DATA, p->tve_cache[i]);
return OPAL_SUCCESS;
}
static void npu2_hw_init(struct npu2 *p)
{
int i;
uint64_t val, size, addr, gpu_min_addr, gpu_max_addr, total_size;
npu2_ioda_reset(&p->phb, false);
/* Enable XTS retry mode */
val = npu2_read(p, NPU2_XTS_CFG);
npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO);
if (!is_p9dd1()) {
val = npu2_read(p, NPU2_XTS_CFG2);
npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA);
}
/* Init memory cache directory (MCD) registers. */
phys_map_get(p->chip_id, GPU_MEM, NPU2_LINKS_PER_CHIP - 1,
&gpu_min_addr, NULL);
phys_map_get(p->chip_id, GPU_MEM, 0, &gpu_max_addr, &size);
gpu_max_addr += size;
/* We assume GPU memory is contiguous from the first possible GPU to the
* last and that the size is the same so best to check that. */
for (i = 0; i < NPU2_LINKS_PER_CHIP; i++) {
uint64_t tmp;
phys_map_get(p->chip_id, GPU_MEM, i, &addr, &tmp);
assert((addr >= gpu_min_addr) && (addr + tmp <= gpu_max_addr));
assert(tmp == size);
}
/* We have two MCDs, so if neccessary we can split the region covered
* across both if total_size is not a power of two. */
total_size = gpu_max_addr - gpu_min_addr;
size = 1ull << ilog2(total_size);
/* Allocate the biggest chunk first as we assume gpu_max_addr has the
* highest alignment. */
addr = gpu_max_addr - size;
val = PPC_BIT(0);
val = SETFIELD(PPC_BITMASK(13, 29), val, (size >> 25) - 1);
val = SETFIELD(PPC_BITMASK(33, 63), val, addr >> 25);
xscom_write(p->chip_id, MCD0_BANK0_CN3, val);
total_size -= size;
if (total_size) {
/* total_size was not a power of two, but the remainder should
* be if all GPUs were assigned the same size. */
assert(is_pow2(total_size));
size = 1ull << ilog2(total_size);
addr -= size;
assert(addr <= gpu_min_addr);
val = PPC_BIT(0);
val = SETFIELD(PPC_BITMASK(13, 29), val, (size >> 25) - 1);
val = SETFIELD(PPC_BITMASK(33, 63), val, addr >> 25);
xscom_write(p->chip_id, MCD1_BANK0_CN3, val);
}
}
static int64_t npu2_map_pe_dma_window_real(struct phb *phb,
uint64_t pe_num,
uint16_t window_id,
uint64_t pci_start_addr,
uint64_t pci_mem_size)
{
struct npu2 *p = phb_to_npu2(phb);
uint64_t end;
uint64_t tve;
/* Sanity check. Each PE has one corresponding TVE */
if (pe_num >= NPU2_MAX_PE_NUM ||
window_id != pe_num)
return OPAL_PARAMETER;
if (pci_mem_size) {
/* Enable */
end = pci_start_addr + pci_mem_size;
/* We have to be 16M aligned */
if ((pci_start_addr & 0x00ffffff) ||
(pci_mem_size & 0x00ffffff))
return OPAL_PARAMETER;
/*
* It *looks* like this is the max we can support (we need
* to verify this. Also we are not checking for rollover,
* but then we aren't trying too hard to protect ourselves
* againt a completely broken OS.
*/
if (end > 0x0003ffffffffffffull)
return OPAL_PARAMETER;
/*
* Put start address bits 49:24 into TVE[52:53]||[0:23]
* and end address bits 49:24 into TVE[54:55]||[24:47]
* and set TVE[51]
*/
tve = (pci_start_addr << 16) & (0xffffffull << 40);
tve |= (pci_start_addr >> 38) & (3ull << 10);
tve |= (end >> 8) & (0xfffffful << 16);
tve |= (end >> 40) & (3ull << 8);
tve |= PPC_BIT(51);
} else {
/* Disable */
tve = 0;
}
npu2_ioda_sel(p, NPU2_ATS_IODA_TBL_TVT, window_id, false);
out_be64(p->regs + NPU2_ATS_IODA_DATA, tve);
p->tve_cache[window_id] = tve;
return OPAL_SUCCESS;
}
static int64_t npu2_map_pe_dma_window(struct phb *phb,
uint64_t pe_num,
uint16_t window_id,
uint16_t tce_levels,
uint64_t tce_table_addr,
uint64_t tce_table_size,
uint64_t tce_page_size)
{
struct npu2 *p = phb_to_npu2(phb);
uint64_t tts_encoded;
uint64_t data64 = 0;
/* Sanity check. Each PE has one corresponding TVE */
if (pe_num >= NPU2_MAX_PE_NUM ||
window_id != pe_num)
return OPAL_PARAMETER;
/*
* Special condition, zero TCE table size used to disable
* the TVE.
*/
if (!tce_table_size) {
npu2_ioda_sel(p, NPU2_ATS_IODA_TBL_TVT, window_id, false);
out_be64(p->regs + NPU2_ATS_IODA_DATA, 0ul);
p->tve_cache[window_id] = 0ul;
return OPAL_SUCCESS;
}
/* Additional arguments validation */
if (tce_levels < 1 ||
tce_levels > 4 ||
!is_pow2(tce_table_size) ||
tce_table_size < 0x1000)
return OPAL_PARAMETER;
/* TCE table size */
data64 = SETFIELD(NPU2_ATS_IODA_TBL_TVT_TTA, 0ul, tce_table_addr >> 12);
tts_encoded = ilog2(tce_table_size) - 11;
if (tts_encoded > 39)
return OPAL_PARAMETER;
data64 = SETFIELD(NPU2_ATS_IODA_TBL_TVT_SIZE, data64, tts_encoded);
/* TCE page size */
switch (tce_page_size) {
case 0x10000: /* 64K */
data64 = SETFIELD(NPU2_ATS_IODA_TBL_TVT_PSIZE, data64, 5);
break;
case 0x1000000: /* 16M */
data64 = SETFIELD(NPU2_ATS_IODA_TBL_TVT_PSIZE, data64, 13);
break;
case 0x10000000: /* 256M */
data64 = SETFIELD(NPU2_ATS_IODA_TBL_TVT_PSIZE, data64, 17);
break;
case 0x1000: /* 4K */
default:
data64 = SETFIELD(NPU2_ATS_IODA_TBL_TVT_PSIZE, data64, 1);
}
/* Number of levels */
data64 = SETFIELD(NPU2_ATS_IODA_TBL_TVT_LEVEL, data64, tce_levels - 1);
/* Update to hardware */
npu2_ioda_sel(p, NPU2_ATS_IODA_TBL_TVT, window_id, false);
out_be64(p->regs + NPU2_ATS_IODA_DATA, data64);