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phb*: Remove the state field in the various phb structures
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We've been carting around this field since the original p7ioc-phb code.
As far as I can tell we never actually use it for anything other than
checking if the PHB has been marked as broken or not. The _FENCED
state is set in a few places, but we never use it in favour of just
checking the MMIO register.

This patch just replaces it with a boolean that indicates if
the PHB has been marked as broken and removes the giant, mostly
wrong, comment explaining it's usage that is copied and pasted
into each phb header file.

Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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@oohal @stewartsmith
oohal authored and stewartsmith committed Mar 22, 2018
1 parent 87f33f4 commit 3e74805
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Showing 7 changed files with 40 additions and 233 deletions.
27 changes: 12 additions & 15 deletions hw/p7ioc-phb.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,7 @@ static int64_t p7ioc_pcicfg_check(struct p7ioc_phb *p, uint32_t bdfn,
return OPAL_HARDWARE;

/* Check PHB state */
if (p->state == P7IOC_PHB_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

return OPAL_SUCCESS;
Expand Down Expand Up @@ -296,7 +296,7 @@ static int64_t p7ioc_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
*pci_error_type = OPAL_EEH_NO_ERROR;

/* Check dead */
if (p->state == P7IOC_PHB_STATE_BROKEN) {
if (p->broken) {
*freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
*pci_error_type = OPAL_EEH_PHB_ERROR;
if (severity)
Expand All @@ -311,7 +311,6 @@ static int64_t p7ioc_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
*pci_error_type = OPAL_EEH_PHB_ERROR;
if (severity)
*severity = OPAL_EEH_SEV_PHB_FENCED;
p->state = P7IOC_PHB_STATE_FENCED;
goto bail;
}

Expand Down Expand Up @@ -372,7 +371,7 @@ static int64_t p7ioc_eeh_next_error(struct phb *phb, uint64_t *first_frozen_pe,
*first_frozen_pe = (uint64_t)-1;

/* Check dead */
if (p->state == P7IOC_PHB_STATE_BROKEN) {
if (p->broken) {
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_PHB_DEAD;
return OPAL_SUCCESS;
Expand All @@ -383,7 +382,6 @@ static int64_t p7ioc_eeh_next_error(struct phb *phb, uint64_t *first_frozen_pe,
/* Should be OPAL_EEH_STOPPED_TEMP_UNAVAIL ? */
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_PHB_FENCED;
p->state = P7IOC_PHB_STATE_FENCED;
p7ioc_phb_set_err_pending(p, false);
return OPAL_SUCCESS;
}
Expand Down Expand Up @@ -2474,7 +2472,7 @@ static void p7ioc_phb_err_interrupt(struct irq_source *is, uint32_t isn)
opal_pci_eeh_set_evt(p->phb.opal_id);

/* If the PHB is broken, go away */
if (p->state == P7IOC_PHB_STATE_BROKEN)
if (p->broken)
return;

/*
Expand All @@ -2483,7 +2481,6 @@ static void p7ioc_phb_err_interrupt(struct irq_source *is, uint32_t isn)
*/
phb_lock(&p->phb);
if (p7ioc_phb_fenced(p)) {
p->state = P7IOC_PHB_STATE_FENCED;
PHBERR(p, "ER error ignored, PHB fenced\n");
phb_unlock(&p->phb);
return;
Expand Down Expand Up @@ -2657,7 +2654,6 @@ void p7ioc_phb_setup(struct p7ioc *ioc, uint8_t index)
p->io_base = ioc->mmio1_win_start + PHBn_IO_BASE(index);
p->m32_base = ioc->mmio2_win_start + PHBn_M32_BASE(index);
p->m64_base = ioc->mmio2_win_start + PHBn_M64_BASE(index);
p->state = P7IOC_PHB_STATE_UNINITIALIZED;
p->phb.scan_map = 0x1; /* Only device 0 to scan */

/* Find P7IOC base location code in IOC */
Expand Down Expand Up @@ -2959,7 +2955,11 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)

PHBDBG(p, "Initializing PHB %x...\n", p->index);

p->state = P7IOC_PHB_STATE_INITIALIZING;
/*
* We re-init the PHB on a creset (and a few other cases)
* so clear the broken flag
*/
p->broken = false;

/* For some reason, the doc wants us to read the version
* register, so let's do it. We shoud probably check that
Expand Down Expand Up @@ -3173,14 +3173,11 @@ int64_t p7ioc_phb_init(struct p7ioc_phb *p)
out_be64(p->regs + PHB_TIMEOUT_CTRL1, 0x1611112010200000UL);
out_be64(p->regs + PHB_TIMEOUT_CTRL2, 0x0000561300000000UL);

/* Mark the PHB as functional which enables all the various sequences */
p->state = P7IOC_PHB_STATE_FUNCTIONAL;

return OPAL_SUCCESS;

failed:
PHBERR(p, "Initialization failed\n");
p->state = P7IOC_PHB_STATE_BROKEN;
p->broken = true;

return OPAL_HARDWARE;
}
Expand All @@ -3206,7 +3203,7 @@ void p7ioc_phb_reset(struct phb *phb)
* notable that the IODA table cache won't be emptied so that we
* can restore them during error recovery.
*/
if (p->state == P7IOC_PHB_STATE_FUNCTIONAL && !fenced) {
if (!p->broken && !fenced) {
PHBDBG(p, " ioda reset ...\n");
p7ioc_ioda_reset(&p->phb, false);
time_wait_ms(100);
Expand Down Expand Up @@ -3247,7 +3244,7 @@ void p7ioc_phb_reset(struct phb *phb)
/* Reset failed, not much to do, maybe add an error return */
if (fenced) {
PHBERR(p, "Reset failed, fence still set !\n");
p->state = P7IOC_PHB_STATE_BROKEN;
p->broken = true;
return;
}

Expand Down
2 changes: 0 additions & 2 deletions hw/p7ioc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -666,8 +666,6 @@ static void p7ioc_create_hub(struct dt_node *np)
for (i = 0; i < P7IOC_NUM_PHBS; i++) {
if (p7ioc_phb_enabled(ioc, i))
p7ioc_phb_setup(ioc, i);
else
ioc->phbs[i].state = P7IOC_PHB_STATE_OFF;
}

/* Now, we do the bulk of the inits */
Expand Down
27 changes: 12 additions & 15 deletions hw/phb3.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,6 @@ static bool phb3_fenced(struct phb3 *p)
xscom_read(p->chip_id, p->pe_xscom + 0x0, &nfir);
if (nfir & PPC_BIT(16)) {
p->flags |= PHB3_AIB_FENCED;
p->state = PHB3_STATE_FENCED;
return true;
}
return false;
Expand Down Expand Up @@ -134,7 +133,7 @@ static int64_t phb3_pcicfg_check(struct phb3 *p, uint32_t bdfn,
return OPAL_HARDWARE;

/* Check PHB state */
if (p->state == PHB3_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

/* Fetch the PE# from cache */
Expand Down Expand Up @@ -1798,7 +1797,7 @@ static int64_t phb3_msi_set_xive(struct irq_source *is, uint32_t isn,
index = p8_irq_to_phb(isn);
ive_num = PHB3_IRQ_NUM(isn);

if (p->state == PHB3_STATE_BROKEN || !p->tbl_rtt)
if (p->broken || !p->tbl_rtt)
return OPAL_HARDWARE;
if (chip != p->chip_id ||
index != p->index ||
Expand Down Expand Up @@ -1908,7 +1907,7 @@ static int64_t phb3_lsi_set_xive(struct irq_source *is, uint32_t isn,
index = p8_irq_to_phb(isn);
irq = PHB3_IRQ_NUM(isn);

if (p->state == PHB3_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

if (chip != p->chip_id ||
Expand Down Expand Up @@ -1953,7 +1952,7 @@ static void phb3_err_interrupt(struct irq_source *is, uint32_t isn)
OPAL_EVENT_PCI_ERROR);

/* If the PHB is broken, go away */
if (p->state == PHB3_STATE_BROKEN)
if (p->broken)
return;

/*
Expand Down Expand Up @@ -2181,7 +2180,7 @@ static int64_t phb3_get_presence_state(struct pci_slot *slot, uint8_t *val)
struct phb3 *p = phb_to_phb3(slot->phb);
uint64_t hp_override;

if (p->state == PHB3_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

/*
Expand Down Expand Up @@ -2675,7 +2674,6 @@ static int64_t phb3_creset(struct pci_slot *slot)
}

error:
p->state = PHB3_STATE_FENCED;
return OPAL_HARDWARE;
}

Expand Down Expand Up @@ -2732,7 +2730,7 @@ static int64_t phb3_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
*pci_error_type = OPAL_EEH_NO_ERROR;

/* Check dead */
if (p->state == PHB3_STATE_BROKEN) {
if (p->broken) {
*freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
*pci_error_type = OPAL_EEH_PHB_ERROR;
if (severity)
Expand Down Expand Up @@ -2788,7 +2786,7 @@ static int64_t phb3_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
int32_t i;
bool frozen_pe = false;

if (p->state == PHB3_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

/* Summary. If nothing, move to clearing the PESTs which can
Expand Down Expand Up @@ -2845,7 +2843,7 @@ static int64_t phb3_eeh_freeze_set(struct phb *phb, uint64_t pe_number,
struct phb3 *p = phb_to_phb3(phb);
uint64_t data;

if (p->state == PHB3_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

if (pe_number >= PHB3_MAX_PE_NUM)
Expand Down Expand Up @@ -2884,7 +2882,7 @@ static int64_t phb3_eeh_next_error(struct phb *phb,
int32_t i, j;

/* If the PHB is broken, we needn't go forward */
if (p->state == PHB3_STATE_BROKEN) {
if (p->broken) {
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_PHB_DEAD;
return OPAL_SUCCESS;
Expand Down Expand Up @@ -3369,7 +3367,7 @@ static int64_t phb3_get_diag_data(struct phb *phb,

if (diag_buffer_len < sizeof(struct OpalIoPhb3ErrorData))
return OPAL_PARAMETER;
if (p->state == PHB3_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

/*
Expand Down Expand Up @@ -4373,15 +4371,15 @@ static void phb3_init_hw(struct phb3 *p, bool first_init)
out_be64(p->regs + PHB_TIMEOUT_CTRL2, 0x2320d71600000000);

/* Mark the PHB as functional which enables all the various sequences */
p->state = PHB3_STATE_FUNCTIONAL;
p->broken = false;

PHBDBG(p, "Initialization complete\n");

return;

failed:
PHBERR(p, "Initialization failed\n");
p->state = PHB3_STATE_BROKEN;
p->broken = true;
}

static void phb3_allocate_tables(struct phb3 *p)
Expand Down Expand Up @@ -4625,7 +4623,6 @@ static void phb3_create(struct dt_node *np)
p->phb.ops = &phb3_ops;
p->phb.phb_type = phb_type_pcie_v3;
p->phb.scan_map = 0x1; /* Only device 0 to scan */
p->state = PHB3_STATE_UNINITIALIZED;

if (!phb3_calculate_windows(p))
return;
Expand Down
28 changes: 13 additions & 15 deletions hw/phb4.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -274,7 +274,7 @@ static int64_t phb4_pcicfg_check(struct phb4 *p, uint32_t bdfn,
return OPAL_HARDWARE;

/* Check PHB state */
if (p->state == PHB4_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

/* Fetch the PE# from cache */
Expand Down Expand Up @@ -2187,7 +2187,7 @@ static int64_t phb4_get_presence_state(struct pci_slot *slot, uint8_t *val)
uint64_t hps, dtctl;

/* Test for PHB in error state ? */
if (p->state == PHB4_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

/* Check hotplug status */
Expand Down Expand Up @@ -2399,7 +2399,6 @@ static bool phb4_fenced(struct phb4 *p)

/* Mark ourselves fenced */
p->flags |= PHB4_AIB_FENCED;
p->state = PHB4_STATE_FENCED;

/* dump capp error registers in case phb was fenced due to capp */
if (nfir_n & XPEC_NEST_STK_PCI_NFIR_CXA_PE_CAPP)
Expand Down Expand Up @@ -2884,7 +2883,7 @@ static int64_t phb4_creset(struct pci_slot *slot)
uint64_t pbcq_status, reg;

/* Don't even try fixing a broken PHB */
if (p->state == PHB4_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

switch (slot->state) {
Expand Down Expand Up @@ -2983,7 +2982,7 @@ static int64_t phb4_creset(struct pci_slot *slot)

error:
/* Mark the PHB as dead and expect it to be removed */
p->state = PHB4_STATE_BROKEN;
p->broken = true;
return OPAL_HARDWARE;
}

Expand Down Expand Up @@ -3087,7 +3086,7 @@ static int64_t phb4_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
*pci_error_type = OPAL_EEH_NO_ERROR;

/* Check dead */
if (p->state == PHB4_STATE_BROKEN) {
if (p->broken) {
*freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
*pci_error_type = OPAL_EEH_PHB_ERROR;
if (severity)
Expand Down Expand Up @@ -3150,7 +3149,7 @@ static int64_t phb4_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
int32_t i;
bool frozen_pe = false;

if (p->state == PHB4_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

/* Summary. If nothing, move to clearing the PESTs which can
Expand Down Expand Up @@ -3207,7 +3206,7 @@ static int64_t phb4_eeh_freeze_set(struct phb *phb, uint64_t pe_number,
struct phb4 *p = phb_to_phb4(phb);
uint64_t data;

if (p->state == PHB4_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

if (pe_number >= p->num_pes)
Expand Down Expand Up @@ -3246,7 +3245,7 @@ static int64_t phb4_eeh_next_error(struct phb *phb,
int32_t i, j;

/* If the PHB is broken, we needn't go forward */
if (p->state == PHB4_STATE_BROKEN) {
if (p->broken) {
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_PHB_DEAD;
return OPAL_SUCCESS;
Expand Down Expand Up @@ -3548,7 +3547,7 @@ static int64_t phb4_get_diag_data(struct phb *phb,

if (diag_buffer_len < sizeof(struct OpalIoPhb4ErrorData))
return OPAL_PARAMETER;
if (p->state == PHB4_STATE_BROKEN)
if (p->broken)
return OPAL_HARDWARE;

/*
Expand Down Expand Up @@ -4689,15 +4688,15 @@ static void phb4_init_hw(struct phb4 *p, bool first_init)
out_be64(p->regs + PHB_PBL_TIMEOUT_CTRL, 0x2013000000000000ull);

/* Mark the PHB as functional which enables all the various sequences */
p->state = PHB4_STATE_FUNCTIONAL;
p->broken = false;

PHBDBG(p, "Initialization complete\n");

return;

failed:
PHBERR(p, "Initialization failed\n");
p->state = PHB4_STATE_BROKEN;
p->broken = true;
}

/* FIXME: Use scoms rather than MMIO incase we are fenced */
Expand Down Expand Up @@ -4954,7 +4953,7 @@ static void phb4_err_interrupt(struct irq_source *is, uint32_t isn)
OPAL_EVENT_PCI_ERROR);

/* If the PHB is broken, go away */
if (p->state == PHB3_STATE_BROKEN)
if (p->broken)
return;

/*
Expand Down Expand Up @@ -5056,7 +5055,6 @@ static void phb4_create(struct dt_node *np)
p->phb.ops = &phb4_ops;
p->phb.phb_type = phb_type_pcie_v4;
p->phb.scan_map = 0x1; /* Only device 0 to scan */
p->state = PHB4_STATE_UNINITIALIZED;

if (!phb4_calculate_windows(p))
return;
Expand Down Expand Up @@ -5229,7 +5227,7 @@ static void phb4_create(struct dt_node *np)
return;

failed:
p->state = PHB4_STATE_BROKEN;
p->broken = true;

/* Tell Linux it's broken */
dt_add_property_string(np, "status", "error");
Expand Down

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