xive: Ensure pressure relief interrupts are disabled

We don't use them and we hijack the VP field with their configuration to store the EQ reference, so make sure the kernel or guest can't turn them back on by doing MMIO writes to ACK# Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
open-power · Sep 13, 2017 · 443b564 · 443b564
1 parent 1cf6072
commit 443b564
Show file tree

Hide file tree

Showing 2 changed files with 3 additions and 0 deletions.
diff --git a/hw/xive.c b/hw/xive.c
@@ -1623,6 +1623,8 @@ static bool xive_config_init(struct xive *x)
 #endif
 	val |= PC_TCTXT_CHIPID_OVERRIDE;
 	val |= PC_TCTXT_CFG_TARGET_EN;
+	/* Disable pressure relief as we hijack the field in the VPs */
+	val &= ~PC_TCTXT_CFG_STORE_ACK;
 	val = SETFIELD(PC_TCTXT_CHIPID, val, x->block_id);
 	xive_regw(x, PC_TCTXT_CFG, val);
 	xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val);

diff --git a/include/xive.h b/include/xive.h
@@ -75,6 +75,7 @@
 #define PC_TCTXT_CFG		0x400
 #define  PC_TCTXT_CFG_BLKGRP_EN		PPC_BIT(0)
 #define  PC_TCTXT_CFG_TARGET_EN		PPC_BIT(1)
+#define  PC_TCTXT_CFG_STORE_ACK		PPC_BIT(3)
 #define  PC_TCTXT_CFG_HARD_CHIPID_BLK	PPC_BIT(8)
 #define  PC_TCTXT_CHIPID_OVERRIDE	PPC_BIT(9)
 #define  PC_TCTXT_CHIPID		PPC_BITMASK(12,15)