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This defines the size of our VP space which is constrained by the definition of the END structure in the XIVE architecture for POWER9: #define EQ_W6_NVT_BLOCK PPC_BITMASK32(9,12) #define EQ_W6_NVT_INDEX PPC_BITMASK32(13,31) The NVT/VP id is returned to the hypervisor by the OPAL call opal_xive_get_vp_info() and later pushed in W2 of the OS CAM line when a vCPU is dispatched on an HW thread. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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