power-mgmt : occ : Add 'freq-domain-mask' DT property

Add a new device-tree property freq-domain-indicator to define group of
CPUs which would share same frequency. This property has been added under
power-mgmt node. It is a bitmask.

Bitwise AND is taken between this bitmask value and PIR of cpu. All the
CPUs lying in the same frequency domain will have same result for AND.

For example, For POWER9, 0xFFF0 indicates quad wide frequency domain.
Taking AND with the PIR of CPUs will yield us frequency domain which is
quad wise distribution as last 4 bits have been masked which represent the
cores.

Similarly, 0xFFF8 will represent core wide frequency domain for P8.

Also, Add a new device-tree property domain-runs-at which will denote the
strategy OCC is using to change the frequency of a frequency-domain. There
can be two strategy - FREQ_MOST_RECENTLY_SET and FREQ_MAX_IN_DOMAIN.

FREQ_MOST_RECENTLY_SET : the OCC sets the frequency of the quad to the most
recent frequency value requested by the CPUs in the quad.

FREQ_MAX_IN_DOMAIN : the OCC sets the frequency of the CPUs in
the Quad to the maximum of the latest frequency requested by each of
the component cores.

Signed-off-by: Abhishek Goel <huntbag@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>

doc/device-tree/ibm,opal/power-mgt/occ.rst

@@ -37,3 +37,40 @@ ibm,pstate-vcss ibm,pstate-vdds
 These properties list a voltage-identifier of each of the pstates listed in
 ibm,pstate-ids for the Vcs and Vdd values used for that pstate in that chip.
 Each VID is a single byte.
+
+ibm,opal/power-mgt/freq-domain-mask
+-----------------------------------
+
+This property is a bitmask which will have different value depending upon the
+generation of the processor. Frequency domain would indicate group of CPUs
+which would share same frequency. Bitwise AND is taken between this bitmask
+value and PIR of cpu. All the CPUs lying in the same frequency domain will have
+same result for AND. Thus frequency management can be done based on frequency
+domain. A frequency domain may be a core or a quad, etc depending upon the
+generation of the processor.
+
+For example, for POWER8 0xFFF8 indicates core wide frequency domain. Taking AND
+with the PIR of CPUs will yield us a frequency domain which is core wide
+distribution as last 3 bits have been masked which represent the threads.
+
+For POWER9, 0xFFF0 indicates quad wide frequency domain. Taking AND with
+the PIR of CPUs will yield us frequency domain which is quad wise
+distribution as last 4 bits have been masked which represent the cores.
+
+ibm,opal/power-mgt/domain-runs-at
+---------------------------------
+
+There are two strategies in which the OCC can change the frequency of the cores
+in the quad on P9.
+1) FREQ_MAX_IN_DOMAIN : the OCC sets the frequency of the quad to the maximum
+of the latest frequency requested by each of the component cores.
+2) FREQ_MOST_RECENTLY_SET : the OCC sets the frequency of the quad to the most
+recent frequency value requested by the CPUs in the quad
+
+In case of P8, the domain is the core and the strategy by default is
+FREQ_MOST_RECENTLY_SET since the PMCRs of the threads in the core are mirrored.
+However on P9, the domain is quad and the strategy is FREQ_MAX_IN_DOMAIN since
+each core has its own PMCR.
+
+domain-runs-at denotes the strategy which OCC is using to change the frequency
+of a frequency domain.

hw/occ.c

@@ -48,6 +48,11 @@
 #define MAX_OPAL_CMD_DATA_LENGTH	4090
 #define MAX_OCC_RSP_DATA_LENGTH		8698
 
+#define P8_PIR_CORE_MASK		0xFFF8
+#define P9_PIR_QUAD_MASK		0xFFF0
+#define FREQ_MAX_IN_DOMAIN		0
+#define FREQ_MOST_RECENTLY_SET		1
+
 /**
  * OCC-OPAL Shared Memory Region
  *
@@ -498,6 +503,15 @@ static bool add_cpu_pstate_properties(int *pstate_nom)
 	u8 nr_pstates;
 	bool ultra_turbo_supported;
 	int i, major, minor;
+	u8 domain_runs_at;
+	u32 freq_domain_mask;
+
+	/* TODO Firmware plumbing required so as to have two modes to set
+	 * PMCR based on max in domain or most recently used. As of today,
+	 * it is always max in domain for P9.
+	 */
+	domain_runs_at = 0;
+	freq_domain_mask = 0;
 
 	prlog(PR_DEBUG, "OCC: CPU pstate state device tree init\n");
 
@@ -670,6 +684,14 @@ static bool add_cpu_pstate_properties(int *pstate_nom)
 		return false;
 	}
 
+	if (proc_gen == proc_gen_p8) {
+		freq_domain_mask = P8_PIR_CORE_MASK;
+		domain_runs_at = FREQ_MOST_RECENTLY_SET;
+	} else if (proc_gen == proc_gen_p9) {
+		freq_domain_mask = P9_PIR_QUAD_MASK;
+		domain_runs_at = FREQ_MAX_IN_DOMAIN;
+	}
+
 	/* Add the device-tree entries */
 	dt_add_property(power_mgt, "ibm,pstate-ids", dt_id,
 			nr_pstates * sizeof(u32));
@@ -678,6 +700,8 @@ static bool add_cpu_pstate_properties(int *pstate_nom)
 	dt_add_property_cells(power_mgt, "ibm,pstate-min", pmin);
 	dt_add_property_cells(power_mgt, "ibm,pstate-nominal", pnom);
 	dt_add_property_cells(power_mgt, "ibm,pstate-max", pmax);
+	dt_add_property_cells(power_mgt, "freq-domain-mask", freq_domain_mask);
+	dt_add_property_cells(power_mgt, "domain-runs-at", domain_runs_at);
 
 	free(dt_freq);
 	free(dt_id);