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Hello, Dr. Jiao.
We are using your image. My modification
I saw that the top file for side_ch had a predefined data bit width and thought I could modify it directly. So, I tried modifying the side_ch IP Core of the FPGA , I want to use it to get more information at the same time, because I want to add some functionality, I tried to change the bit width of the data from side_ch to PS using DMA directly from 64bit to 128bit, and the width of the device tree to 128bit, but when using Linux script:./side_ch_ctl g.The side_info_count does not increase, which means no data send to PS.
Our Board/hardware type:
Based on fcms2+zedboard.
My debug efforts:
After a lot fruitless attempts, I looked at some of the signals using ILA and found that the AXI, which might be used to control the SIDE_CH cycle for data acquisition, might not be working properly.
The above is the online Debug diagram of my modified FPGA project.
The above is yours.
The key is that the signal line slv_reg_wren, which should appear periodically.After the modification, it only becomes high the first time I execute insmod side_ch.ko and./side_ch_ctrl g. I guess:Perhaps AXI is not working properly because DMA is passing 128 bits at a time but only 64bit is coming out?
Could you give me some suggestions about changing the data bit width?
The text was updated successfully, but these errors were encountered:
First of all, check your ARM CPU spec of your board, to confirm it support 128bit DMA or not.
Instead of extend 64 to 128, you should consider change the RAM and state machine inside side_ch (and python script on computer) to put more 64bits into single DMA transaction (more 64bit words per transaction).
First of all, check your ARM CPU spec of your board, to confirm it support 128bit DMA or not.
Instead of extend 64 to 128, you should consider change the RAM and state machine inside side_ch (and python script on computer) to put more 64bits into single DMA transaction (more 64bit words per transaction).
Thank you. I'll give it a try. I've definitely got more 64bit data.
Hello, Dr. Jiao.
We are using your image.
My modification
I saw that the top file for side_ch had a predefined data bit width and thought I could modify it directly. So, I tried modifying the side_ch IP Core of the FPGA , I want to use it to get more information at the same time, because I want to add some functionality, I tried to change the bit width of the data from side_ch to PS using DMA directly from 64bit to 128bit, and the width of the device tree to 128bit, but when using Linux script:
./side_ch_ctl g
.The side_info_count does not increase, which means no data send to PS.Our Board/hardware type:
Based on fcms2+zedboard.
My debug efforts:
After a lot fruitless attempts, I looked at some of the signals using ILA and found that the AXI, which might be used to control the SIDE_CH cycle for data acquisition, might not be working properly.
The above is the online Debug diagram of my modified FPGA project.
The above is yours.
The key is that the signal line slv_reg_wren, which should appear periodically.After the modification, it only becomes high the first time I execute
insmod side_ch.ko
and./side_ch_ctrl g.
I guess:Perhaps AXI is not working properly because DMA is passing 128 bits at a time but only 64bit is coming out?
Could you give me some suggestions about changing the data bit width?
The text was updated successfully, but these errors were encountered: