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pdp11_cpu.c
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pdp11_cpu.c
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/* pdp11_cpu.c: PDP-11 CPU simulator
Copyright (c) 1993-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
cpu PDP-11 CPU
30-Nov022 RMS More 11/45,11/70 trap hackery (Walter Mueller)
29-Nov-22 RMS Trap stack abort must clear other traps/aborts (Walter Mueller)
23-Oct-22 RMS Fixed priority of MME traps (Walter Mueller)
02-Sep-22 RMS Fixed handling of PDR<A> (Walter Mueller)
31-Aug-22 RMS MMR0<15:13> != 0 locks bits<15:13> (Walter Mueller)
MMR0<12> = 1 disables further traps (Walter Mueller)
25-Aug-22 RMS 11/45,70 clear MMR1 in trap sequence (Walter Mueller)
23-Aug-22 RMS 11/45,70 detect red stack abort before memory write
in JSR, MFPx (Walter Mueller)
20-Aug-22 RMS MMR1 reads as 0 on subset memory mmgt systems
11/44, 45, 70 track PC changes (Walter Mueller)
J11 tracks PC changes on -(PC) and @-(PC)
25-Jul-22 RMS Removed deprecated CPU models (Q22, UHR11, URH70)
04-Jun-18 RMS Removed CPU model entries for UC15 (Mark Pizzolato)
04-Dec-16 RMS Removed duplicate IDLE entries in MTAB
30-Aug-16 RMS Fixed overloading of -d in ex/mod
14-Mar-16 RMS Added UC15 support
06-Mar-16 RMS Fixed bug in history virtual addressing
30-Dec-15 RMS Added NOBEVENT option for 11/03, 11/23
29-Dec-15 RMS Call build_dib_tab during reset (Mark Pizzolato)
05-Dec-13 RMS Fixed bug in CSM (John Dundas)
23-Oct-13 RMS Fixed PS behavior on initialization and boot
10-Apr-13 RMS MMR1 does not track PC changes (Johnny Billquist)
29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato)
19-Mar-12 RMS Fixed declaration of sim_switches (Mark Pizzolato)
29-Dec-08 RMS Fixed failure to clear cpu_bme on RESET (Walter Mueller)
22-Apr-08 RMS Fixed MMR0 treatment in RESET (Walter Mueller)
02-Feb-08 RMS Fixed DMA memory address limit test (John Dundas)
28-Apr-07 RMS Removed clock initialization
27-Oct-06 RMS Added idle support
18-Oct-06 RMS Fixed bug in ASH -32 C value
24-May-06 RMS Added instruction history
03-May-06 RMS Fixed XOR operand fetch order for 11/70-style systems
22-Sep-05 RMS Fixed declarations (Sterling Garwood)
16-Aug-05 RMS Fixed C++ declaration and cast problems
19-May-05 RMS Replaced WAIT clock queue check with API call
19-Jan-05 RMS Fixed bug(s) in RESET for 11/70 (Tim Chapman)
22-Dec-04 RMS Fixed WAIT to work in all modes (John Dundas)
02-Oct-04 RMS Added model emulation
25-Jan-04 RMS Removed local debug logging support
29-Dec-03 RMS Formalized 18b Qbus support
21-Dec-03 RMS Added autoconfiguration controls
05-Jun-03 RMS Fixed bugs in memory size table
12-Mar-03 RMS Added logical name support
01-Feb-03 RMS Changed R display to follow PSW<rs>, added SP display
19-Jan-03 RMS Changed mode definitions for Apple Dev Kit conflict
05-Jan-03 RMS Added memory size restore support
17-Oct-02 RMS Fixed bug in examine/deposit (Hans Pufal)
08-Oct-02 RMS Revised to build dib_tab dynamically
Added SHOW IOSPACE
09-Sep-02 RMS Added KW11P support
14-Jul-02 RMS Fixed bug in MMR0 error status load
03-Jun-02 RMS Fixed relocation add overflow, added PS<15:12> = 1111
special case logic to MFPI and removed it from MTPI
(John Dundas)
29-Apr-02 RMS More fixes to DIV and ASH/ASHC (John Dundas)
28-Apr-02 RMS Fixed bugs in illegal instruction 000010 and in
write-only memory pages (Wolfgang Helbig)
21-Apr-02 RMS Fixed bugs in DIV by zero, DIV overflow, TSTSET, RTS,
ASHC -32, and red zone trap (John Dundas)
04-Mar-02 RMS Changed double operand evaluation order for M+
23-Feb-02 RMS Fixed bug in MAINT, CPUERR, MEMERR read
28-Jan-02 RMS Revised for multiple timers; fixed calc_MMR1 macros
06-Jan-02 RMS Revised enable/disable support
30-Dec-01 RMS Added old PC queue
25-Dec-01 RMS Cleaned up sim_inst declarations
11-Dec-01 RMS Moved interrupt debug code
07-Dec-01 RMS Revised to use new breakpoint package
08-Nov-01 RMS Moved I/O to external module
26-Oct-01 RMS Revised to use symbolic definitions for IO page
15-Oct-01 RMS Added debug logging
08-Oct-01 RMS Fixed bug in revised interrupt logic
07-Sep-01 RMS Revised device disable and interrupt mechanisms
26-Aug-01 RMS Added DZ11 support
10-Aug-01 RMS Removed register from declarations
17-Jul-01 RMS Fixed warning from VC++ 6.0
01-Jun-01 RMS Added DZ11 interrupts
23-Apr-01 RMS Added RK611 support
05-Apr-01 RMS Added TS11/TSV05 support
05-Mar-01 RMS Added clock calibration support
11-Feb-01 RMS Added DECtape support
25-Jan-01 RMS Fixed 4M memory definition (Eric Smith)
14-Apr-99 RMS Changed t_addr to unsigned
18-Aug-98 RMS Added CIS support
09-May-98 RMS Fixed bug in DIV overflow test
19-Jan-97 RMS Added RP/RM support
06-Apr-96 RMS Added dynamic memory sizing
29-Feb-96 RMS Added TM11 support
17-Jul-94 RMS Corrected updating of MMR1 if MMR0 locked
The register state for the PDP-11 is:
REGFILE[0:5][0] general register set
REGFILE[0:5][1] alternate general register set
STACKFILE[4] stack pointers for kernel, supervisor, unused, user
PC program counter
PSW processor status word
<15:14> = CM current processor mode
<13:12> = PM previous processor mode
<11> = RS register set select
<8> = FPD first part done (CIS)
<7:5> = IPL interrupt priority level
<4> = TBIT trace trap enable
<3:0> = NZVC condition codes
FR[0:5] floating point accumulators
FPS floating point status register
FEC floating exception code
FEA floating exception address
MMR0,1,2,3 memory management control registers
APRFILE[0:63] memory management relocation registers for
kernel, supervisor, unused, user
<31:16> = PAR processor address registers
<15:0> = PDR processor data registers
PIRQ processor interrupt request register
CPUERR CPU error register
MEMERR memory system error register
CCR cache control register
MAINT maintenance register
HITMISS cache status register
SR switch register
DR display register
The PDP-11 has many instruction formats:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ double operand
| opcode | source spec | dest spec | 010000:067777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 110000:167777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ register + operand
| opcode | src reg| dest spec | 004000:004777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 070000:077777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ single operand
| opcode | dest spec | 000100:000177
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 000300:000377
005000:007777
105000:107777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ single register
| opcode |dest reg| 000200:000207
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 000230:000237
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ no operand
| opcode | 000000:000007
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ branch
| opcode | branch displacement | 000400:003477
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 100000:103477
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ EMT/TRAP
| opcode | trap code | 104000:104777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ cond code operator
| opcode | immediate | 000240:000277
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
An operand specifier consists of an addressing mode and a register.
The addressing modes are:
0 register direct R op = R
1 register deferred (R) op = M[R]
2 autoincrement (R)+ op = M[R]; R = R + length
3 autoincrement deferred @(R)+ op = M[M[R]]; R = R + 2
4 autodecrement -(R) R = R - length; op = M[R]
5 autodecrement deferred @-(R) R = R - 2; op = M[M[R]]
6 displacement d(R) op = M[R + disp]
7 displacement deferred @d(R) op = M[M[R + disp]]
There are eight general registers, R0-R7. R6 is the stack pointer,
R7 the PC. The combination of addressing modes with R7 yields:
27 immediate #n op = M[PC]; PC = PC + 2
37 absolute @#n op = M[M[PC]]; PC = PC + 2
67 relative d(PC) op = M[PC + disp]
77 relative deferred @d(PC) op = M[M[PC + disp]]
This routine is the instruction decode routine for the PDP-11. It
is called from the simulator control program to execute instructions
in simulated memory, starting at the simulated PC. It runs until an
enabled exception is encountered.
General notes:
1. Virtual address format. PDP-11 memory management uses the 16b
virtual address, the type of reference (instruction or data), and
the current mode, to construct the 22b physical address. To
package this conveniently, the simulator uses a 19b pseudo virtual
address, consisting of the 16b virtual address prefixed with the
current mode and ispace/dspace indicator. These are precalculated
as isenable and dsenable for ispace and dspace, respectively, and
must be recalculated whenever MMR0, MMR3, or PSW<cm> changes.
2. Traps and interrupts. Variable trap_req bit-encodes all possible
traps. In addition, an interrupt pending bit is encoded as the
lowest priority trap. Traps are processed by trap_vec and trap_clear,
which provide the vector and subordinate traps to clear, respectively.
Array int_req[0:7] bit encodes all possible interrupts. It is masked
under the interrupt priority level, ipl. If any interrupt request
is not masked, the interrupt bit is set in trap_req. While most
interrupts are handled centrally, a device can supply an interrupt
acknowledge routine.
3. PSW handling. The PSW is kept as components, for easier access.
Because the PSW can be explicitly written as address 17777776,
all instructions must update PSW before executing their last write.
4. Adding I/O devices. These modules must be modified:
pdp11_defs.h add device address and interrupt definitions
pdp11_sys.c add to sim_devices table entry
*/
/* Definitions */
#include "pdp11_defs.h"
#include "pdp11_cpumod.h"
#define PCQ_SIZE 64 /* must be 2**n */
#define PCQ_MASK (PCQ_SIZE - 1)
#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC
#define calc_is(md) ((md) << VA_V_MODE)
#define calc_ds(md) (calc_is((md)) | ((MMR3 & dsmask[(md)])? VA_DS: 0))
/* Register change tracking actually goes into variable reg_mods; from there
it is copied into MMR1 if that register is not currently locked. */
#define calc_MMR1(val) ((reg_mods)? (((val) << 8) | reg_mods): (val))
#define GET_SIGN_W(v) (((v) >> 15) & 1)
#define GET_SIGN_B(v) (((v) >> 7) & 1)
#define GET_Z(v) ((v) == 0)
#define JMP_PC(x) PCQ_ENTRY; PC = (x)
#define BRANCH_F(x) PCQ_ENTRY; PC = (PC + (((x) + (x)) & 0377)) & 0177777
#define BRANCH_B(x) PCQ_ENTRY; PC = (PC + (((x) + (x)) | 0177400)) & 0177777
#define UNIT_V_MSIZE (UNIT_V_UF + 0) /* dummy */
#define UNIT_MSIZE (1u << UNIT_V_MSIZE)
#define HIST_MIN 64
#define HIST_MAX (1u << 18)
#define HIST_VLD 1 /* make PC odd */
#define HIST_ILNT 4 /* max inst length */
typedef struct {
uint16 pc;
uint16 psw;
uint16 src;
uint16 dst;
uint16 sp;
uint16 pad;
uint16 inst[HIST_ILNT];
} InstHistory;
/* Global state */
uint16 *M = NULL; /* memory */
int32 REGFILE[6][2] = { {0} }; /* R0-R5, two sets */
int32 STACKFILE[4] = { 0 }; /* SP, four modes */
int32 saved_PC = 0; /* program counter */
int32 R[8] = { 0 }; /* working registers */
int32 PSW = 0; /* PSW */
int32 cm = 0; /* current mode */
int32 pm = 0; /* previous mode */
int32 rs = 0; /* register set */
int32 fpd = 0; /* first part done */
int32 ipl = 0; /* int pri level */
int32 tbit = 0; /* trace flag */
int32 N = 0, Z = 0, V = 0, C = 0; /* condition codes */
int32 wait_state = 0; /* wait state */
int32 trap_req = 0; /* trap requests */
int32 int_req[IPL_HLVL] = { 0 }; /* interrupt requests */
int32 PIRQ = 0; /* programmed int req */
int32 STKLIM = 0; /* stack limit */
fpac_t FR[6] = { {0} }; /* fp accumulators */
int32 FPS = 0; /* fp status */
int32 FEC = 0; /* fp exception code */
int32 FEA = 0; /* fp exception addr */
int32 APRFILE[64] = { 0 }; /* PARs/PDRs */
int32 MMR0 = 0; /* MMR0 - status */
int32 MMR1 = 0; /* MMR1 - R+/-R */
int32 MMR2 = 0; /* MMR2 - saved PC */
int32 MMR3 = 0; /* MMR3 - 22b status */
int32 cpu_bme = 0; /* bus map enable */
int32 cpu_astop = 0; /* address stop */
int32 isenable = 0, dsenable = 0; /* i, d space flags */
int32 stop_trap = 1; /* stop on trap */
int32 stop_vecabort = 1; /* stop on vec abort */
int32 stop_spabort = 1; /* stop on SP abort */
int32 autcon_enb = 1; /* autoconfig enable */
uint32 cpu_model = INIMODEL; /* CPU model */
uint32 cpu_type = 1u << INIMODEL; /* model as bit mask */
uint32 cpu_opt = INIOPTNS; /* CPU options */
uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
int32 pcq_p = 0; /* PC queue ptr */
REG *pcq_r = NULL; /* PC queue reg ptr */
jmp_buf save_env; /* abort handler */
int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
int32 dsmask[4] = { MMR3_KDS, MMR3_SDS, 0, MMR3_UDS }; /* dspace enables */
int16 inst_pc; /* PC of current instr */
int32 inst_psw; /* PSW at instr. start */
int16 reg_mods; /* reg deltas */
int32 last_pa; /* pa from ReadMW/ReadMB */
int32 saved_sim_interval; /* saved at inst start */
t_stat reason; /* stop reason */
extern int32 CPUERR, MAINT;
extern CPUTAB cpu_tab[];
/* Function declarations */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs);
t_stat cpu_set_hist (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat cpu_show_virt (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat cpu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *cpu_description (DEVICE *dptr);
int32 GeteaB (int32 spec);
int32 GeteaW (int32 spec);
int32 relocR (int32 addr);
int32 relocW (int32 addr);
void relocR_test (int32 va, int32 apridx);
void relocW_test (int32 va, int32 apridx);
int32 relocC (int32 va, int32 sw);
t_bool PLF_test (int32 va, int32 apr);
void reloc_abort (int32 err, int32 apridx);
int32 ReadE (int32 addr);
int32 ReadW (int32 addr);
int32 ReadB (int32 addr);
int32 ReadCW (int32 addr);
int32 ReadMW (int32 addr);
int32 ReadMB (int32 addr);
int32 PReadW (int32 addr);
int32 PReadB (int32 addr);
void WriteW (int32 data, int32 addr);
void WriteB (int32 data, int32 addr);
void WriteCW (int32 data, int32 addr);
void PWriteW (int32 data, int32 addr);
void PWriteB (int32 data, int32 addr);
void set_r_display (int32 rs, int32 cm);
t_stat CPU_wr (int32 data, int32 addr, int32 access);
void set_stack_trap (int32 adr);
int32 get_PSW (void);
void put_PSW (int32 val, t_bool prot);
void put_PIRQ (int32 val);
extern void fp11 (int32 IR);
extern t_stat cis11 (int32 IR);
extern t_stat fis11 (int32 IR);
extern t_stat build_dib_tab (void);
extern t_stat iopageR (int32 *data, uint32 addr, int32 access);
extern t_stat iopageW (int32 data, uint32 addr, int32 access);
extern int32 calc_ints (int32 nipl, int32 trq);
extern int32 get_vector (int32 nipl);
/* Trap data structures */
int32 trap_vec[TRAP_V_MAX] = { /* trap req to vector */
VEC_RED, VEC_ODD, VEC_NXM, VEC_MME,
VEC_PAR, VEC_PRV, VEC_ILL, VEC_BPT,
VEC_IOT, VEC_EMT, VEC_TRAP, VEC_TRC,
VEC_YEL, VEC_PWRFL, VEC_FPE
};
t_bool trap_load_mmr2[TRAP_V_MAX + 1] = { /* do trap requests load MMR2? */
TRUE, TRUE, TRUE, TRUE,
TRUE, FALSE, FALSE, FALSE,
FALSE, FALSE, FALSE, TRUE,
TRUE, TRUE, TRUE, TRUE /* last is interrupt */
};
int32 trap_clear[TRAP_V_MAX] = { /* trap clears */
TRAP_RED+TRAP_ODD+TRAP_NXM+TRAP_PAR+TRAP_YEL+TRAP_TRC+TRAP_MME, /* red stack abort */
TRAP_ODD+TRAP_NXM+TRAP_PAR+TRAP_YEL+TRAP_TRC+TRAP_MME, /* odd address abort */
TRAP_NXM+TRAP_PAR+TRAP_YEL+TRAP_TRC+TRAP_MME, /* nxm abort */
TRAP_MME+TRAP_PAR+TRAP_YEL+TRAP_TRC, /* mme abort or trap */
TRAP_PAR+TRAP_YEL+TRAP_TRC,
TRAP_PRV+TRAP_TRC, /* instruction traps */
TRAP_ILL+TRAP_TRC, /* occur in fetch or */
TRAP_BPT+TRAP_TRC, /* initial decode */
TRAP_IOT+TRAP_TRC, /* no yelstk possible */
TRAP_EMT+TRAP_TRC,
TRAP_TRAP+TRAP_TRC,
TRAP_TRC,
TRAP_YEL,
TRAP_PWRFL,
TRAP_FPE
};
/* CPU data structures
cpu_dev CPU device descriptor
cpu_unit CPU unit descriptor
cpu_reg CPU register list
cpu_mod CPU modifier list
*/
UNIT cpu_unit = { UDATA (NULL, UNIT_FIX|UNIT_BINK, INIMEMSIZE) };
const char *psw_modes[] = {"K", "S", "E", "U"};
BITFIELD psw_bits[] = {
BIT(C), /* Carry */
BIT(V), /* Overflow */
BIT(Z), /* Zero */
BIT(N), /* Negative */
BIT(TBIT), /* trace trap */
BITFFMT(IPL,3,%d), /* IPL */
BIT(FPD), /* First Part Done */
BITNCF(2), /* MBZ */
BIT(RS), /* Register Set */
BITFNAM(PM,2,psw_modes), /* Previous Access Mode */
BITFNAM(CM,2,psw_modes), /* Current Access Mode */
ENDBITS
};
REG cpu_reg[] = {
{ ORDATAD (PC, saved_PC, 16, "Program Counter") },
{ ORDATAD (R0, REGFILE[0][0], 16, "General Purpose R0") },
{ ORDATAD (R1, REGFILE[1][0], 16, "General Purpose R1") },
{ ORDATAD (R2, REGFILE[2][0], 16, "General Purpose R2") },
{ ORDATAD (R3, REGFILE[3][0], 16, "General Purpose R3") },
{ ORDATAD (R4, REGFILE[4][0], 16, "General Purpose R4") },
{ ORDATAD (R5, REGFILE[5][0], 16, "General Purpose R5") },
{ ORDATAD (SP, STACKFILE[MD_KER], 16, "Stack Pointer"), },
{ ORDATAD (R00, REGFILE[0][0], 16, "Register File R00") },
{ ORDATAD (R01, REGFILE[1][0], 16, "Register File R01") },
{ ORDATAD (R02, REGFILE[2][0], 16, "Register File R02") },
{ ORDATAD (R03, REGFILE[3][0], 16, "Register File R03") },
{ ORDATAD (R04, REGFILE[4][0], 16, "Register File R04") },
{ ORDATAD (R05, REGFILE[5][0], 16, "Register File R05") },
{ ORDATAD (R10, REGFILE[0][1], 16, "Register File R10") },
{ ORDATAD (R11, REGFILE[1][1], 16, "Register File R11") },
{ ORDATAD (R12, REGFILE[2][1], 16, "Register File R12") },
{ ORDATAD (R13, REGFILE[3][1], 16, "Register File R13") },
{ ORDATAD (R14, REGFILE[4][1], 16, "Register File R14") },
{ ORDATAD (R15, REGFILE[5][1], 16, "Register File R15") },
{ ORDATAD (KSP, STACKFILE[MD_KER], 16, "Kernel Stack Pointer" ) },
{ ORDATAD (SSP, STACKFILE[MD_SUP], 16, "Supervisor Stack Pointer" ) },
{ ORDATAD (USP, STACKFILE[MD_USR], 16, "User Stack Pointer" ) },
{ ORDATADF(PSW, PSW, 16, "Processor Status Word", psw_bits) },
{ GRDATAD (CM, PSW, 8, 2, PSW_V_CM, "Current Mode") },
{ GRDATAD (PM, PSW, 8, 2, PSW_V_PM, "Previous Mode") },
{ FLDATAD (RS, PSW, PSW_V_RS, "Register Set") },
{ FLDATAD (FPD, PSW, PSW_V_FPD, "First Part Done") },
{ GRDATAD (IPL, PSW, 8, 3, PSW_V_IPL, "Interrupt Priority Level") },
{ FLDATAD (T, PSW, PSW_V_TBIT, "Trace Trap") },
{ FLDATAD (N, PSW, PSW_V_N, "Condition Code: Negative") },
{ FLDATAD (Z, PSW, PSW_V_Z, "Condition Code: Zero") },
{ FLDATAD (V, PSW, PSW_V_V, "Condition Code: Overflow") },
{ FLDATAD (C, PSW, PSW_V_C, "Condition Code: Carry") },
{ ORDATAD (PIRQ, PIRQ, 16, "programmed interrupt requests") },
{ ORDATAD (STKLIM, STKLIM, 16, "stack limit") },
{ ORDATAD (FAC0H, FR[0].h, 32, "Floating Point: R0 High") },
{ ORDATAD (FAC0L, FR[0].l, 32, "Floating Point: R0 Low") },
{ ORDATAD (FAC1H, FR[1].h, 32, "Floating Point: R1 High") },
{ ORDATAD (FAC1L, FR[1].l, 32, "Floating Point: R1 Low") },
{ ORDATAD (FAC2H, FR[2].h, 32, "Floating Point: R2 High") },
{ ORDATAD (FAC2L, FR[2].l, 32, "Floating Point: R2 Low") },
{ ORDATAD (FAC3H, FR[3].h, 32, "Floating Point: R3 High") },
{ ORDATAD (FAC3L, FR[3].l, 32, "Floating Point: R3 Low") },
{ ORDATAD (FAC4H, FR[4].h, 32, "Floating Point: R4 High") },
{ ORDATAD (FAC4L, FR[4].l, 32, "Floating Point: R4 Low") },
{ ORDATAD (FAC5H, FR[5].h, 32, "Floating Point: R5 High") },
{ ORDATAD (FAC5L, FR[5].l, 32, "Floating Point: R5 Low") },
{ ORDATAD (FPS, FPS, 16, "floating point status") },
{ ORDATAD (FEA, FEA, 16, "floating exception address") },
{ ORDATAD (FEC, FEC, 4, "floating exception code") },
{ ORDATAD (MMR0, MMR0, 16, "MMR0 - Status") },
{ ORDATAD (MMR1, MMR1, 16, "MMR1 - R+/-R") },
{ ORDATAD (MMR2, MMR2, 16, "MMR2 - saved PC") },
{ ORDATAD (MMR3, MMR3, 16, "MMR3 - 22b status") },
{ GRDATA (KIPAR0, APRFILE[000], 8, 16, 16) },
{ GRDATA (KIPDR0, APRFILE[000], 8, 16, 0) },
{ GRDATA (KIPAR1, APRFILE[001], 8, 16, 16) },
{ GRDATA (KIPDR1, APRFILE[001], 8, 16, 0) },
{ GRDATA (KIPAR2, APRFILE[002], 8, 16, 16) },
{ GRDATA (KIPDR2, APRFILE[002], 8, 16, 0) },
{ GRDATA (KIPAR3, APRFILE[003], 8, 16, 16) },
{ GRDATA (KIPDR3, APRFILE[003], 8, 16, 0) },
{ GRDATA (KIPAR4, APRFILE[004], 8, 16, 16) },
{ GRDATA (KIPDR4, APRFILE[004], 8, 16, 0) },
{ GRDATA (KIPAR5, APRFILE[005], 8, 16, 16) },
{ GRDATA (KIPDR5, APRFILE[005], 8, 16, 0) },
{ GRDATA (KIPAR6, APRFILE[006], 8, 16, 16) },
{ GRDATA (KIPDR6, APRFILE[006], 8, 16, 0) },
{ GRDATA (KIPAR7, APRFILE[007], 8, 16, 16) },
{ GRDATA (KIPDR7, APRFILE[007], 8, 16, 0) },
{ GRDATA (KDPAR0, APRFILE[010], 8, 16, 16) },
{ GRDATA (KDPDR0, APRFILE[010], 8, 16, 0) },
{ GRDATA (KDPAR1, APRFILE[011], 8, 16, 16) },
{ GRDATA (KDPDR1, APRFILE[011], 8, 16, 0) },
{ GRDATA (KDPAR2, APRFILE[012], 8, 16, 16) },
{ GRDATA (KDPDR2, APRFILE[012], 8, 16, 0) },
{ GRDATA (KDPAR3, APRFILE[013], 8, 16, 16) },
{ GRDATA (KDPDR3, APRFILE[013], 8, 16, 0) },
{ GRDATA (KDPAR4, APRFILE[014], 8, 16, 16) },
{ GRDATA (KDPDR4, APRFILE[014], 8, 16, 0) },
{ GRDATA (KDPAR5, APRFILE[015], 8, 16, 16) },
{ GRDATA (KDPDR5, APRFILE[015], 8, 16, 0) },
{ GRDATA (KDPAR6, APRFILE[016], 8, 16, 16) },
{ GRDATA (KDPDR6, APRFILE[016], 8, 16, 0) },
{ GRDATA (KDPAR7, APRFILE[017], 8, 16, 16) },
{ GRDATA (KDPDR7, APRFILE[017], 8, 16, 0) },
{ GRDATA (SIPAR0, APRFILE[020], 8, 16, 16) },
{ GRDATA (SIPDR0, APRFILE[020], 8, 16, 0) },
{ GRDATA (SIPAR1, APRFILE[021], 8, 16, 16) },
{ GRDATA (SIPDR1, APRFILE[021], 8, 16, 0) },
{ GRDATA (SIPAR2, APRFILE[022], 8, 16, 16) },
{ GRDATA (SIPDR2, APRFILE[022], 8, 16, 0) },
{ GRDATA (SIPAR3, APRFILE[023], 8, 16, 16) },
{ GRDATA (SIPDR3, APRFILE[023], 8, 16, 0) },
{ GRDATA (SIPAR4, APRFILE[024], 8, 16, 16) },
{ GRDATA (SIPDR4, APRFILE[024], 8, 16, 0) },
{ GRDATA (SIPAR5, APRFILE[025], 8, 16, 16) },
{ GRDATA (SIPDR5, APRFILE[025], 8, 16, 0) },
{ GRDATA (SIPAR6, APRFILE[026], 8, 16, 16) },
{ GRDATA (SIPDR6, APRFILE[026], 8, 16, 0) },
{ GRDATA (SIPAR7, APRFILE[027], 8, 16, 16) },
{ GRDATA (SIPDR7, APRFILE[027], 8, 16, 0) },
{ GRDATA (SDPAR0, APRFILE[030], 8, 16, 16) },
{ GRDATA (SDPDR0, APRFILE[030], 8, 16, 0) },
{ GRDATA (SDPAR1, APRFILE[031], 8, 16, 16) },
{ GRDATA (SDPDR1, APRFILE[031], 8, 16, 0) },
{ GRDATA (SDPAR2, APRFILE[032], 8, 16, 16) },
{ GRDATA (SDPDR2, APRFILE[032], 8, 16, 0) },
{ GRDATA (SDPAR3, APRFILE[033], 8, 16, 16) },
{ GRDATA (SDPDR3, APRFILE[033], 8, 16, 0) },
{ GRDATA (SDPAR4, APRFILE[034], 8, 16, 16) },
{ GRDATA (SDPDR4, APRFILE[034], 8, 16, 0) },
{ GRDATA (SDPAR5, APRFILE[035], 8, 16, 16) },
{ GRDATA (SDPDR5, APRFILE[035], 8, 16, 0) },
{ GRDATA (SDPAR6, APRFILE[036], 8, 16, 16) },
{ GRDATA (SDPDR6, APRFILE[036], 8, 16, 0) },
{ GRDATA (SDPAR7, APRFILE[037], 8, 16, 16) },
{ GRDATA (SDPDR7, APRFILE[037], 8, 16, 0) },
{ GRDATA (UIPAR0, APRFILE[060], 8, 16, 16) },
{ GRDATA (UIPDR0, APRFILE[060], 8, 16, 0) },
{ GRDATA (UIPAR1, APRFILE[061], 8, 16, 16) },
{ GRDATA (UIPDR1, APRFILE[061], 8, 16, 0) },
{ GRDATA (UIPAR2, APRFILE[062], 8, 16, 16) },
{ GRDATA (UIPDR2, APRFILE[062], 8, 16, 0) },
{ GRDATA (UIPAR3, APRFILE[063], 8, 16, 16) },
{ GRDATA (UIPDR3, APRFILE[063], 8, 16, 0) },
{ GRDATA (UIPAR4, APRFILE[064], 8, 16, 16) },
{ GRDATA (UIPDR4, APRFILE[064], 8, 16, 0) },
{ GRDATA (UIPAR5, APRFILE[065], 8, 16, 16) },
{ GRDATA (UIPDR5, APRFILE[065], 8, 16, 0) },
{ GRDATA (UIPAR6, APRFILE[066], 8, 16, 16) },
{ GRDATA (UIPDR6, APRFILE[066], 8, 16, 0) },
{ GRDATA (UIPAR7, APRFILE[067], 8, 16, 16) },
{ GRDATA (UIPDR7, APRFILE[067], 8, 16, 0) },
{ GRDATA (UDPAR0, APRFILE[070], 8, 16, 16) },
{ GRDATA (UDPDR0, APRFILE[070], 8, 16, 0) },
{ GRDATA (UDPAR1, APRFILE[071], 8, 16, 16) },
{ GRDATA (UDPDR1, APRFILE[071], 8, 16, 0) },
{ GRDATA (UDPAR2, APRFILE[072], 8, 16, 16) },
{ GRDATA (UDPDR2, APRFILE[072], 8, 16, 0) },
{ GRDATA (UDPAR3, APRFILE[073], 8, 16, 16) },
{ GRDATA (UDPDR3, APRFILE[073], 8, 16, 0) },
{ GRDATA (UDPAR4, APRFILE[074], 8, 16, 16) },
{ GRDATA (UDPDR4, APRFILE[074], 8, 16, 0) },
{ GRDATA (UDPAR5, APRFILE[075], 8, 16, 16) },
{ GRDATA (UDPDR5, APRFILE[075], 8, 16, 0) },
{ GRDATA (UDPAR6, APRFILE[076], 8, 16, 16) },
{ GRDATA (UDPDR6, APRFILE[076], 8, 16, 0) },
{ GRDATA (UDPAR7, APRFILE[077], 8, 16, 16) },
{ GRDATA (UDPDR7, APRFILE[077], 8, 16, 0) },
{ BRDATAD (IREQ, int_req, 8, 32, IPL_HLVL, "interrupt pending flags, IPL 0 to 7"), REG_RO },
{ ORDATAD (TRAPS, trap_req, TRAP_V_MAX, "trap pending flags") },
{ FLDATAD (WAIT, wait_state, 0, "wait state enable flag") },
{ ORDATAD (STOP_TRAPS, stop_trap, TRAP_V_MAX, "stop on trap flags") },
{ FLDATAD (STOP_VECA, stop_vecabort, 0, "stop on read abort in trap or interrupt") },
{ FLDATAD (STOP_SPA, stop_spabort, 0, "stop on stack abort in trap or interrupt") },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ BRDATAD (PCQ, pcq, 8, 16, PCQ_SIZE, "PC prior to last jump, branch, or interrupt; Most recent PC change first"), REG_RO+REG_CIRC },
{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
{ ORDATAD (WRU, sim_int_char, 8, "interrupt character") },
{ ORDATA (MODEL, cpu_model, 16), REG_HRO },
{ ORDATA (OPTIONS, cpu_opt, 32), REG_HRO },
{ NULL}
};
MTAB cpu_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "TYPE", NULL,
NULL, &cpu_show_model },
#if !defined (UC15)
{ MTAB_XTD|MTAB_VDV, MOD_1103, NULL, "11/03", &cpu_set_model, NULL, NULL, "Set CPU type to 11/03" },
{ MTAB_XTD|MTAB_VDV, MOD_1104, NULL, "11/04", &cpu_set_model, NULL, NULL, "Set CPU type to 11/04" },
{ MTAB_XTD|MTAB_VDV, MOD_1105, NULL, "11/05", &cpu_set_model, NULL, NULL, "Set CPU type to 11/05" },
{ MTAB_XTD|MTAB_VDV, MOD_1120, NULL, "11/20", &cpu_set_model, NULL, NULL, "Set CPU type to 11/20" },
{ MTAB_XTD|MTAB_VDV, MOD_1123, NULL, "11/23", &cpu_set_model, NULL, NULL, "Set CPU type to 11/23" },
{ MTAB_XTD|MTAB_VDV, MOD_1123P, NULL, "11/23+", &cpu_set_model, NULL, NULL, "Set CPU type to 11/23+" },
{ MTAB_XTD|MTAB_VDV, MOD_1124, NULL, "11/24", &cpu_set_model, NULL, NULL, "Set CPU type to 11/24" },
{ MTAB_XTD|MTAB_VDV, MOD_1134, NULL, "11/34", &cpu_set_model, NULL, NULL, "Set CPU type to 11/34" },
{ MTAB_XTD|MTAB_VDV, MOD_1140, NULL, "11/40", &cpu_set_model, NULL, NULL, "Set CPU type to 11/40" },
{ MTAB_XTD|MTAB_VDV, MOD_1144, NULL, "11/44", &cpu_set_model, NULL, NULL, "Set CPU type to 11/44" },
{ MTAB_XTD|MTAB_VDV, MOD_1145, NULL, "11/45", &cpu_set_model, NULL, NULL, "Set CPU type to 11/45" },
{ MTAB_XTD|MTAB_VDV, MOD_1153, NULL, "11/53", &cpu_set_model, NULL, NULL, "Set CPU type to 11/53" },
{ MTAB_XTD|MTAB_VDV, MOD_1160, NULL, "11/60", &cpu_set_model, NULL, NULL, "Set CPU type to 11/60" },
{ MTAB_XTD|MTAB_VDV, MOD_1170, NULL, "11/70", &cpu_set_model, NULL, NULL, "Set CPU type to 11/70" },
{ MTAB_XTD|MTAB_VDV, MOD_1173, NULL, "11/73", &cpu_set_model, NULL, NULL, "Set CPU type to 11/73" },
{ MTAB_XTD|MTAB_VDV, MOD_1173B, NULL, "11/73B", &cpu_set_model, NULL, NULL, "Set CPU type to 11/73B" },
{ MTAB_XTD|MTAB_VDV, MOD_1183, NULL, "11/83", &cpu_set_model, NULL, NULL, "Set CPU type to 11/83" },
{ MTAB_XTD|MTAB_VDV, MOD_1184, NULL, "11/84", &cpu_set_model, NULL, NULL, "Set CPU type to 11/84" },
{ MTAB_XTD|MTAB_VDV, MOD_1193, NULL, "11/93", &cpu_set_model, NULL, NULL, "Set CPU type to 11/93" },
{ MTAB_XTD|MTAB_VDV, MOD_1194, NULL, "11/94", &cpu_set_model, NULL, NULL, "Set CPU type to 11/94" },
{ MTAB_XTD|MTAB_VDV, MOD_1173, NULL, "Q22", &cpu_set_model, NULL, NULL, "deprecated: same as 11/73" },
{ MTAB_XTD|MTAB_VDV, MOD_1184, NULL, "URH11", &cpu_set_model, NULL, NULL, "deprecated: same as 11/84" },
{ MTAB_XTD|MTAB_VDV, MOD_1170, NULL, "URH70", &cpu_set_model, NULL, NULL, "deprecated: same as 11/70" },
{ MTAB_XTD|MTAB_VDV, MOD_1145, NULL, "U18", &cpu_set_model, NULL, NULL, "deprecated: same as 11/45" },
{ MTAB_XTD|MTAB_VDV, OPT_EIS, NULL, "EIS", &cpu_set_opt, NULL, NULL, "enable EIS instructions" },
{ MTAB_XTD|MTAB_VDV, OPT_EIS, NULL, "NOEIS", &cpu_clr_opt, NULL, NULL, "disable EIS instructions" },
{ MTAB_XTD|MTAB_VDV, OPT_FIS, NULL, "FIS", &cpu_set_opt, NULL, NULL, "enable FIS instructions" },
{ MTAB_XTD|MTAB_VDV, OPT_FIS, NULL, "NOFIS", &cpu_clr_opt, NULL, NULL, "disable FIS instructions" },
{ MTAB_XTD|MTAB_VDV, OPT_FPP, NULL, "FPP", &cpu_set_opt, NULL, NULL, "enable FPP instructions" },
{ MTAB_XTD|MTAB_VDV, OPT_FPP, NULL, "NOFPP", &cpu_clr_opt, NULL, NULL, "disable FPP instructions" },
{ MTAB_XTD|MTAB_VDV, OPT_CIS, NULL, "CIS", &cpu_set_opt, NULL, NULL, "enable CIS instructions" },
{ MTAB_XTD|MTAB_VDV, OPT_CIS, NULL, "NOCIS", &cpu_clr_opt, NULL, NULL, "disable CIS instructions" },
{ MTAB_XTD|MTAB_VDV, OPT_MMU, NULL, "MMU", &cpu_set_opt, NULL, NULL, "enable MMU functionality" },
{ MTAB_XTD|MTAB_VDV, OPT_MMU, NULL, "NOMMU", &cpu_clr_opt, NULL, NULL, "disable MMU functionality" },
{ MTAB_XTD|MTAB_VDV, OPT_BVT, NULL, "BEVENT", &cpu_set_opt, NULL, NULL, "Enable BEVENT line (11/03, 11/23 only)" },
{ MTAB_XTD|MTAB_VDV, OPT_BVT, NULL, "NOBEVENT", &cpu_clr_opt, NULL, NULL, "Disable BEVENT line (11/03, 11/23 only)" },
{ UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size, NULL, NULL, "Set memory size to 8Kb"},
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size, NULL, NULL, "Set memory size to 16Kb"},
{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size, NULL, NULL, "Set memory size to 24Kb"},
{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size, NULL, NULL, "Set memory size to 32Kb"},
{ UNIT_MSIZE, 40960, NULL, "40K", &cpu_set_size, NULL, NULL, "Set memory size to 40Kb"},
{ UNIT_MSIZE, 49152, NULL, "48K", &cpu_set_size, NULL, NULL, "Set memory size to 48Kb"},
{ UNIT_MSIZE, 57344, NULL, "56K", &cpu_set_size, NULL, NULL, "Set memory size to 56Kb"},
{ UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size, NULL, NULL, "Set memory size to 64Kb"},
{ UNIT_MSIZE, 98304, NULL, "96K", &cpu_set_size, NULL, NULL, "Set memory size to 96Kb"},
{ UNIT_MSIZE, 131072, NULL, "128K", &cpu_set_size, NULL, NULL, "Set memory size to 128Kb"},
{ UNIT_MSIZE, 196608, NULL, "192K", &cpu_set_size, NULL, NULL, "Set memory size to 192Kb"},
{ UNIT_MSIZE, 221184, NULL, "216K", &cpu_set_size, NULL, NULL, "Set memory size to 216Kb"},
{ UNIT_MSIZE, 262144, NULL, "256K", &cpu_set_size, NULL, NULL, "Set memory size to 256Kb"},
{ UNIT_MSIZE, 393216, NULL, "384K", &cpu_set_size, NULL, NULL, "Set memory size to 384Kb"},
{ UNIT_MSIZE, 524288, NULL, "512K", &cpu_set_size, NULL, NULL, "Set memory size to 512Kb"},
{ UNIT_MSIZE, 786432, NULL, "768K", &cpu_set_size, NULL, NULL, "Set memory size to 768Kb"},
{ UNIT_MSIZE, 1048576, NULL, "1024K", &cpu_set_size, NULL, NULL, "Set memory size to 1Mb"},
{ UNIT_MSIZE, 1572864, NULL, "1536K", &cpu_set_size, NULL, NULL, "Set memory size to 1536Kb"},
{ UNIT_MSIZE, 2097152, NULL, "2048K", &cpu_set_size, NULL, NULL, "Set memory size to 2Mb"},
{ UNIT_MSIZE, 3145728, NULL, "3072K", &cpu_set_size, NULL, NULL, "Set memory size to 3Mb"},
{ UNIT_MSIZE, 4186112, NULL, "4096K", &cpu_set_size, NULL, NULL, "Set memory size to 4Mb"},
{ UNIT_MSIZE, 1048576, NULL, "1M", &cpu_set_size, NULL, NULL, "Set memory size to 1Mb"},
{ UNIT_MSIZE, 2097152, NULL, "2M", &cpu_set_size, NULL, NULL, "Set memory size to 2Mb"},
{ UNIT_MSIZE, 3145728, NULL, "3M", &cpu_set_size, NULL, NULL, "Set memory size to 3Mb"},
{ UNIT_MSIZE, 4186112, NULL, "4M", &cpu_set_size, NULL, NULL, "Set memory size to 4Mb"},
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon, NULL, "Enable/Display Auto Configuration" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL, NULL, "Disable Auto Configuration" },
#else
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size, NULL, NULL, "Set memory size to 16Kb"},
{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size, NULL, NULL, "Set memory size to 24Kb"},
#endif
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace, NULL, "Show I/O space address assignments" },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle, NULL, "Enable/Display idle detection" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL, NULL, "Disable idle detection" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP|MTAB_NC, 0, "HISTORY", "HISTORY=n",
&cpu_set_hist, &cpu_show_hist, NULL, "Enable/Display instruction history" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
NULL, &cpu_show_virt, NULL, "Display address translation" },
{ 0 }
};
BRKTYPTAB cpu_breakpoints [] = {
BRKTYPE('E',"Execute Instruction at Virtual Address"),
BRKTYPE('P',"Execute Instruction at Physical Address"),
BRKTYPE('R',"Read from Virtual Address"),
BRKTYPE('S',"Read from Physical Address"),
BRKTYPE('W',"Write to Virtual Address"),
BRKTYPE('X',"Write to Physical Address"),
{ 0 }
};
DEVICE cpu_dev = {
"CPU", &cpu_unit, cpu_reg, cpu_mod,
1, 8, 22, 2, 8, 16,
&cpu_ex, &cpu_dep, &cpu_reset,
&cpu_boot, NULL, NULL,
NULL, DEV_DYNM, 0,
NULL, &cpu_set_size, NULL,
&cpu_help, NULL, NULL, &cpu_description,
cpu_breakpoints
};
t_value pdp11_pc_value (void)
{
return (t_value)PC;
}
t_stat sim_instr (void)
{
int abortval, i;
volatile int32 trapea; /* used by setjmp */
InstHistory *hst_ent = NULL;
sim_vm_pc_value = &pdp11_pc_value;
/* Restore register state
1. PSW components
2. Active register file based on PSW<rs>
3. Active stack pointer based on PSW<cm>
4. Memory management control flags
5. Interrupt system
*/
reason = build_dib_tab (); /* build, chk dib_tab */
if (reason != SCPE_OK)
return reason;
if (MEMSIZE >= (cpu_tab[cpu_model].maxm - IOPAGESIZE)) /* mem size >= max - io page? */
MEMSIZE = cpu_tab[cpu_model].maxm - IOPAGESIZE; /* max - io page */
cpu_type = 1u << cpu_model; /* reset type mask */
cpu_bme = (MMR3 & MMR3_BME) && (cpu_opt & OPT_UBM); /* map enabled? */
PC = saved_PC;
put_PSW (PSW, 0); /* set PSW, call calc_xs */
for (i = 0; i < 6; i++)
R[i] = REGFILE[i][rs];
SP = STACKFILE[cm];
isenable = calc_is (cm);
dsenable = calc_ds (cm);
put_PIRQ (PIRQ); /* rewrite PIRQ */
STKLIM = STKLIM & STKLIM_RW; /* clean up STKLIM */
MMR0 = MMR0 & ~MMR0_IC; /* usually off */
trap_req = calc_ints (ipl, trap_req); /* upd int req */
trapea = 0;
reason = 0;
/* Abort handling
If an abort occurs in memory management or memory access, the lower
level routine executes a longjmp to this area OUTSIDE the main
simulation loop. The longjmp specifies a trap mask which is OR'd
into the trap_req register. Simulation then resumes at the fetch
phase, and the trap is sprung.
Aborts which occur within a trap sequence (trapea != 0) require
special handling. If the abort occured on the stack pushes, and
the mode (encoded in trapea) is kernel, an "emergency" kernel
stack is created at 4, and a red zone stack trap taken.
All variables used in setjmp processing, or assumed to be valid
after setjmp, must be volatile or global.
*/
abortval = setjmp (save_env); /* set abort hdlr */
if (abortval == ABRT_BKPT) {
/* Breakpoint encountered. */
reason = STOP_IBKPT;
/* Print a message reporting the type and address if it is not a
plain virtual PC (instruction execution) breakpoint. */
if (sim_brk_match_type != BPT_PCVIR)
sim_messagef (reason, "\r\n%s", sim_brk_message());
/* Restore the PC and sim_interval. */
PC = inst_pc;
sim_interval = saved_sim_interval;
/* Restore PSW and the broken-out condition code values, provided
FPD is not currently set. If it is, that means the instruction
is interruptible and breakpoints are treated as continuation
rather than replay. */
if (!fpd) {
PSW = inst_psw;
put_PSW (inst_psw, 0);
}
/* Undo register changes. */
while (reg_mods) {
int rnum = reg_mods & 7;
int delta = (reg_mods >> 3) & 037;
reg_mods >>= 8;
if (delta & 020) /* negative delta */
delta = -(-delta & 037); /* get signed value */
if (rnum != 7)
R[rnum] -= delta;
}
}
else {
if (abortval != 0) {
trap_req = trap_req | abortval; /* or in trap flag */
if ((trapea > 0) && stop_vecabort)
reason = STOP_VECABORT;
if ((trapea < 0) && /* stack push abort? */
(CPUT (STOP_STKA) || stop_spabort))
reason = STOP_SPABORT;
if (trapea == ~MD_KER) { /* kernel stk abort? */
trap_req = trap_req & ~trap_clear[TRAP_RED];/* clear all traps */
setTRAP (TRAP_RED); /* set red stack trap */
setCPUERR (CPUE_RED);
STACKFILE[MD_KER] = 4;
if (cm == MD_KER)
SP = 4;
}
}
}
/* Main instruction fetch/decode loop
Check for traps or interrupts. If trap, locate the vector and check
for stop condition. If interrupt, locate the vector.
*/
while (reason == 0) {
int32 IR, srcspec, srcreg, dstspec, dstreg;
int32 src, src2, dst, ea;
int32 i, t, sign, oldrs, trapnum;
if (cpu_astop) {
cpu_astop = 0;
reason = SCPE_STOP;
break;
}
AIO_CHECK_EVENT;
if (sim_interval <= 0) { /* intv cnt expired? */
/* Make sure all intermediate state is visible in simh registers */
PSW = get_PSW ();
for (i = 0; i < 6; i++)
REGFILE[i][rs] = R[i];
STACKFILE[cm] = SP;
saved_PC = PC & 0177777;
pcq_r->qptr = pcq_p; /* update pc q ptr */
set_r_display (rs, cm);
reason = sim_process_event (); /* process events */
/* restore simh register contents into running variables */
PC = saved_PC;
put_PSW (PSW, 0); /* set PSW, call calc_xs */
for (i = 0; i < 6; i++)
R[i] = REGFILE[i][rs];
SP = STACKFILE[cm];
isenable = calc_is (cm);
dsenable = calc_ds (cm);
put_PIRQ (PIRQ); /* rewrite PIRQ */
STKLIM = STKLIM & STKLIM_RW; /* clean up STKLIM */
MMR0 = MMR0 | MMR0_IC; /* usually on */
trap_req = calc_ints (ipl, trap_req); /* recalc int req */
continue;
} /* end if sim_interval */
if (trap_req) { /* check traps, ints */
trapea = 0; /* assume srch fails */
if ((t = trap_req & TRAP_ALL)) { /* if a trap */
for (trapnum = 0; trapnum < TRAP_V_MAX; trapnum++) {
if ((t >> trapnum) & 1) { /* trap set? */
trapea = trap_vec[trapnum]; /* get vec, clr */
trap_req = trap_req & ~trap_clear[trapnum];
if ((stop_trap >> trapnum) & 1) /* stop on trap? */
reason = trapnum + 1;
break;
} /* end if t & 1 */
} /* end for */
} /* end if t */
else {
trapea = get_vector (ipl); /* get int vector */
trapnum = TRAP_V_MAX; /* defang stk trap */
} /* end else t */
if (trapea == 0) { /* nothing to do? */
trap_req = calc_ints (ipl, 0); /* recalculate */
continue; /* back to fetch */
} /* end if trapea */
/* Process a trap or interrupt
1. Exit wait state
2. Save the current SP and PSW
3. Read the new PC, new PSW from trapea, kernel data space
4. Get the mode and stack selected by the new PSW
5. Push the old PC and PSW on the new stack
6. Update SP, PSW, and PC
7. If not stack overflow, check for stack overflow
If the MMU registers are not frozen, the 11/45 and 11/70 will
also clear MMR1 and store the trap vector in MMR2, <except>
for the four instruction traps (EMT, TRAP, IOT, BPT).
*/
wait_state = 0; /* exit wait state */
STACKFILE[cm] = SP;
PSW = get_PSW (); /* assemble PSW */
oldrs = rs;
if ((CPUT (HAS_MMTR)) && (update_MM)) { /* 45,70, not frozen? */
MMR1 = 0; /* clear MMR1 */
if (trap_load_mmr2[trapnum]) /* load MMR2? */
MMR2 = trapea; /* save vector */
}
src = ReadCW (trapea | calc_ds (MD_KER)); /* new PC */
src2 = ReadCW ((trapea + 2) | calc_ds (MD_KER)); /* new PSW */
t = (src2 >> PSW_V_CM) & 03; /* new cm */
trapea = ~t; /* flag pushes */
WriteCW (PSW, ((STACKFILE[t] - 2) & 0177777) | calc_ds (t));
WriteCW (PC, ((STACKFILE[t] - 4) & 0177777) | calc_ds (t));
trapea = 0; /* clear trap flag */
src2 = (src2 & ~PSW_PM) | (cm << PSW_V_PM); /* insert prv mode */
put_PSW (src2, 0); /* call calc_is,ds */
if (rs != oldrs) { /* if rs chg, swap */
for (i = 0; i < 6; i++) {
REGFILE[i][oldrs] = R[i];
R[i] = REGFILE[i][rs];
}
}
SP = (STACKFILE[cm] - 4) & 0177777; /* update SP, PC */
isenable = calc_is (cm);
dsenable = calc_ds (cm);
trap_req = calc_ints (ipl, trap_req);
JMP_PC (src);
if ((cm == MD_KER) && (SP < (STKLIM + STKL_Y)) &&
(trapnum != TRAP_V_RED) && (trapnum != TRAP_V_YEL))
set_stack_trap (SP);
continue; /* end if traps */
}
/* Fetch and decode next instruction */
if (tbit)
setTRAP (TRAP_TRC);
if (wait_state) { /* wait state? */
sim_idle (TMR_CLK, TRUE);
continue;
}
reg_mods = 0;
inst_pc = PC;
/* Save PSW also because condition codes need to be preserved. We
just save the whole PSW because that is sufficient. If
restoring is needed, both the PSW and the components that need
to be restored are handled explicitly. */
inst_psw = get_PSW ();
saved_sim_interval = sim_interval;
if (BPT_SUMM_PC) { /* possible breakpoint */
t_addr pa = relocC (PC, 0); /* relocate PC */
if (sim_brk_test (PC, BPT_PCVIR) || /* Normal PC breakpoint? */
sim_brk_test (pa, BPT_PCPHY)) /* Physical Address breakpoint? */
ABORT (ABRT_BKPT); /* stop simulation */
}
if (update_MM) { /* if mm not frozen */
MMR1 = 0;
MMR2 = PC;
}
IR = ReadE (PC | isenable); /* fetch instruction */
sim_interval = sim_interval - 1;
srcspec = (IR >> 6) & 077; /* src, dst specs */
dstspec = IR & 077;
srcreg = (srcspec <= 07); /* src, dst = rmode? */
dstreg = (dstspec <= 07);
if (hst_lnt) { /* record history? */
t_value val;
uint32 i;
static int32 swmap[4] = {
SWMASK ('K') | SWMASK ('V'), SWMASK ('S') | SWMASK ('V'),
SWMASK ('U') | SWMASK ('V'), SWMASK ('U') | SWMASK ('V')
};
hst_ent = &hst[hst_p];
hst_ent->pc = PC | HIST_VLD;
hst_ent->sp = SP;
hst_ent->psw = get_PSW ();
hst_ent->src = 0;
hst_ent->dst = 0;
hst_ent->inst[0] = IR;
for (i = 1; i < HIST_ILNT; i++) {
if (cpu_ex (&val, (PC + (i << 1)) & 0177777, &cpu_unit, swmap[cm & 03]))
hst_ent->inst[i] = 0;